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SCC511653

更新时间： 2024-09-24 14:59:27

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
12页	354K
描述
NXP 32-bit MCU, Power Arch, PBGA 388

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SCC511653 数据手册

Freescale Semiconductor, Inc.

Product Brief

MPC555PB/D

Rev. 3, 2/2003

MPC555 Product Brief

This document provides an overview of the MPC555 microcontroller, including a block

diagram showing the major modular components and sections that list the major features. The

MPC555 member of the Freescale MPC500 RISC Microcontroller family.

Table 1. MPC555 Features

Device

Flash

Code Compression

MPC555

448 Kbytes

Code compression not supported

Introduction

The MPC555 device offers the following features:

•

PowerPC™ core with floating-point unit

26 Kbytes fast RAM and 6 Kbytes TPU microcode RAM

448 Kbytes Flash EEPROM with 5-V programming

5-V I/O system

Serial system: queued serial multi-channel module (QSMCM), dual CAN 2.0B

controller

modules (TouCAN^TM

)

•

50-channel timer system: dual time processor units (TPU3), modular I/O system

(MIOS1)

•

32 analog inputs: dual queued analog-to-digital converters (QADC64)

Submicron HCMOS (CDR1) technology

272-pin plastic ball grid array (PBGA) packaging

40-MHz operation, -40 °C to 125 °C with dual supply (3.3 V, 5 V) (-55 °C to 125 °C

for the suffix A device)

•

32-bit architecture (PowerPC ISA architecture compliant)

Core performance measured at 52.7-Kbyte Dhrystones (v2.1) @ 40 MHz

Fully static, low power operation

Integrated double-precision floating-point unit

Precise exception model

12 3 4 5 6 7...12

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