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SCANSTA112VS PDF预览

SCANSTA112VS

更新时间: 2024-02-15 14:52:16
品牌 Logo 应用领域
美国国家半导体 - NSC 复用器微控制器和处理器外围集成电路uCs集成电路uPs集成电路
页数 文件大小 规格书
15页 299K
描述
7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer

SCANSTA112VS 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:TFQFP, TQFP100,.63SQ针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.13
外部数据总线宽度:JESD-30 代码:S-PQFP-G100
JESD-609代码:e4长度:14 mm
湿度敏感等级:3端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TFQFP
封装等效代码:TQFP100,.63SQ封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Other Microprocessor ICs
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

SCANSTA112VS 数据手册

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May 2004  
SCANSTA112  
7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer  
n 7 IEEE 1149.1-compatible configurable local scan ports  
n Bi-directional Backplane and LSP0 ports are  
interchangeable slave ports  
n Capable of ignoring TRST of the backplane port when it  
becomes the slave.  
n Stitcher Mode bypasses level 1 and 2 protocols  
n Mode Register0 allows local TAPs to be bypassed,  
selected for insertion into the scan chain individually, or  
serially in groups of two or three  
General Description  
The SCANSTA112 extends the IEEE Std. 1149.1 test bus  
into a multidrop test bus environment. The advantage of a  
multidrop approach over a single serial scan chain is im-  
proved test throughput and the ability to remove a board  
from the system and retain test access to the remaining  
modules. Each SCANSTA112 supports up to  
IEEE1149.1 scan chains which can be accessed individually  
or combined serially.  
7 local  
n Transparent Mode can be enabled with a single  
instruction to conveniently buffer the backplane IEEE  
1149.1 pins to those on a single local scan port  
n General purpose local port passthrough bits are useful  
for delivering write pulses for Flash programming or  
monitoring device status.  
Addressing is accomplished by loading the instruction regis-  
ter with a value matching that of the Slot inputs. Backplane  
and inter-board testing can easily be accomplished by park-  
ing the local TAP Controllers in one of the stable TAP Con-  
troller states via a Park instruction. The 32-bit TCK counter  
enables built in self test operations to be performed on one  
port while other scan chains are simultaneously tested.  
n Known Power-up state  
n TRST on all local scan ports  
n 32-bit TCK counter  
n 16-bit LFSR Signature Compactor  
n Local TAPs can become TRI-STATE via the OE input to  
allow an alternate test master to take control of the local  
TAPs (LSP0-3 have a TRI-STATE notification output)  
n 3.0-3.6V VCC Supply Operation  
The STA112 has a unique feature in that the backplane port  
and the LSP0 port are bidirectional. They can be configured  
to alternatively act as the master or slave port so an alternate  
test master can take control of the entire scan chain network  
from the LSP0 port while the backplane port becomes a  
slave.  
Features  
n Supports live insertion/withdrawal  
n True IEEE 1149.1 hierarchical and multidrop  
addressable capability  
n The 8 address inputs support up to 249 unique slot  
addresses, an Interrogation Address, Broadcast  
Address, and 4 Multi-cast Group Addresses (address  
000000 is reserved)  
20051250  
FIGURE 1. Typical use of SCANSTA112 for board-level management of multiple scan chains.  
© 2004 National Semiconductor Corporation  
DS200512  
www.national.com  

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