Datasheet > 驱动程序和接口 > 线路驱动器或接收器> SCAN92LV090VEHX/NOPB

SCAN92LV090VEHX/NOPB

更新时间： 2024-01-16 17:10:57

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
13页	700K
描述
IC 9 LINE TRANSCEIVER, PQFP64, LQFP-64, Line Driver or Receiver

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SCAN92LV090VEHX/NOPB 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP, QFP64,.47SQ,20	针数：	64
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	1 week
风险等级：	5.37	差分输出：	YES
驱动器位数：	9	高电平输入电流最大值：	0.00002 A
输入特性：	DIFFERENTIAL SCHMITT TRIGGER	接口集成电路类型：	LINE TRANSCEIVER
接口标准：	IEEE 1149.1	JESD-30 代码：	S-PQFP-G64
JESD-609代码：	e3	长度：	10 mm
湿度敏感等级：	3	功能数量：	9
端子数量：	64	最高工作温度：	85 °C
最低工作温度：	-40 °C	最小输出摆幅：	0.24 V
最大输出低电流：	0.002 A	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP64,.47SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	最大接收延迟：	3.9 ns
接收器位数：	9	座面最大高度：	1.6 mm
子类别：	Line Driver or Receivers	最大压摆率：	230 mA
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	最大传输延迟：	2.6 ns
宽度：	10 mm	Base Number Matches：	1

SCAN92LV090VEHX/NOPB 数据手册

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February 2005

SCAN92LV090

9 Channel Bus LVDS Transceiver w/ Boundary SCAN

access port consisting of Test Data Input (TDI), Test Data

General Description

Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and

The SCAN92LV090A is one in a series of Bus LVDS trans-

the optional Test Reset (TRST).

ceivers designed specifically for the high speed, low power

proprietary backplane or cable interfaces. The device oper-

ates from a single 3.3V power supply and includes nine

differential line drivers and nine receivers. To minimize bus

loading, the driver outputs and receiver inputs are internally

connected. The separate I/O of the logic side allows for loop

back support. The device also features a flow through pin out

which allows easy PCB routing for short stubs between its

pins and the connector.

Features

n IEEE 1149.1 (JTAG) Compliant

n Bus LVDS Signaling

n Low power CMOS design

n High Signaling Rate Capability (above 100 Mbps)

n 0.1V to 2.3V Common Mode Range for V_ID= 200mV

100 mV Receiver Sensitivity

The driver translates 3V TTL levels (single-ended) to differ-

ential Bus LVDS (BLVDS) output levels. This allows for high

speed operation, while consuming minimal power with re-

duced EMI. In addition, the differential signaling provides

common mode noise rejection of 1V.

n Supports open and terminated failsafe on port pins

n 3.3V operation

n Glitch free power up/down (Driver & Receiver disabled)

n Light Bus Loading (5 pF typical) per Bus LVDS load

n Designed for Double Termination Applications

n Balanced Output Impedance

n Product offered in 64 pin LQFP package and BGA

package

n High impedance Bus pins on power off (V_CC= 0V)

The receiver threshold is less than 100 mV over a 1V

common mode range and translates the differential Bus

LVDS to standard (TTL/CMOS) levels.

This device is compliant with IEEE 1149.1 Standard Test

Access Port and Boundary Scan Architecture with the incor-

poration of the defined boundary-scan test logic and test

Simplified Functional Diagram

10124201

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS101242

www.national.com

12 3 4 5 6 7...13

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