Datasheet > SC97H73FA

SC97H73FA

更新时间： 2024-09-24 21:15:43

品牌	Logo	应用领域
恩智浦 - NXP		驱动输出元件逻辑集成电路
页数	文件大小	规格书
16页	184K
描述
97H SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, LQFP-52

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SC97H73FA 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	52
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	系列：	97H
输入调节：	DIFFERENTIAL MUX	JESD-30 代码：	S-PQFP-G52
长度：	7 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	52	实输出次数：	12
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.25 ns	座面最大高度：	1.6 mm
子类别：	Clock Driver	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	宽度：	7 mm
最小 fmax：	200 MHz	Base Number Matches：	1

SC97H73FA 数据手册

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SEMICONDUCTOR TECHNICAL DATA

SC97H73/D

Rev 0, 10/2003

Freescale Semiconductor, Inc.

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The SC97H73 is a 3.3V or 2.5V compatible, 1:12 PLL based clock

generator targeted for high performance low-skew clock distribution in

mid-range to high-performance networking, computing and telecom

applications. With output frequencies up to 250 MHz and output skews

less than 250 ps the device meets the needs of the most demanding clock

applications.

3.3V 1:12 LVCMOS

PLL CLOCK GENERATOR

Features

• 1:12 PLL based low-voltage clock generator

• 3.3V power supply

• Generates clock signals up to 250 MHz

• Maximum output skew of 250 ps

• Differential PECL reference clock input

• Two LVCMOS PLL reference clock inputs

• External PLL feedback supports zero-delay capability

• Drives up to 24 clock lines

• Internal power–on reset

• Ambient temperature range 0°C to +70°C

• Pin and function compatible to the SC973X

FA SUFFIX

52 LEAD LQFP PACKAGE

CASE 873A

Functional Description

The SC97H73 utilizes PLL technology to frequency lock its outputs

onto an input reference clock. Normal operation of the SC97H73 requires

the connection of the PLL feedback output QFB to feedback input FB_IN

to close the PLL feedback path. The reference clock frequency and the

divider for the feedback path determine the VCO frequency. Both must be

selected to match the VCO frequency range. The SC97H73 supports the

output to input frequency ratios 8:1 and 4:1.

The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The REF_SEL pin

selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock

inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and

diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The

PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The

SC97H73 has an internal power-on reset (POR) circuitry that resets the device at power up.

The SC97H73 is fully 3.3V compatible and requires no external PLL loop filter components. All inputs (except PCLK) accept

LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission

lines. For series terminated transmission lines, each of the SC97H73 outputs can drive one or two traces giving the devices an

effective fanout of 1:24. The device is pin and function compatible to the SC973X and is packaged in a 52-lead LQFP package.

For More Information On This Product,

Go to: www.freescale.com

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