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SC16C850LIET,118 PDF预览

SC16C850LIET,118

更新时间: 2024-11-21 20:10:55
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
54页 233K
描述
SC16C850L - 1.8 V single UART, 16 mode or 68 mode parallel bus interface BGA 36-Pin

SC16C850LIET,118 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:3.50 X 3.50 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, PLASTIC, SOT-912-1, TFBGA-36针数:36
Reach Compliance Code:unknown风险等级:5.75
Base Number Matches:1

SC16C850LIET,118 数据手册

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SC16C850L  
1.8 V single UART, 5 Mbit/s (max.) with 128-byte FIFOs,  
infrared (IrDA) and 16 mode or 68 mode parallel bus interface  
Rev. 04 — 13 December 2007  
Product data sheet  
1. General description  
The SC16C850L is a 1.8 V, low power, single channel Universal Asynchronous Receiver  
and Transmitter (UART) used for serial data communications. Its principal function is to  
convert parallel data into serial data and vice versa. The UART can handle serial data  
rates up to 5 Mbit/s. The SC16C850L is functionally (software) compatible with the  
SC16C650B. SC16C850L can be programmed to operate in extended mode (see  
Section 6.2) where additional advanced UART features are available. The SC16C850L  
UART provides enhanced UART functions with 128-byte FIFOs, modem control interface,  
and IrDA encoder/decoder. On-board status registers provide the user with error  
indications and operational status. System interrupts and modem control features may be  
tailored by software to meet specific user requirements. An internal loopback capability  
allows on-board diagnostics.  
The SC16C850LIBS with Intel (16 mode) or Motorola (68 mode) bus host interface  
operates at 1.8 V and is available in a very small (Micro-UART) HVQFN32 package.  
The SC16C850LIET with Intel (16 mode) bus host interface operates at 1.8 V and is  
available in a very small TFBGA36 package.  
2. Features  
I Single channel high performance UART  
I Intel or Motorola bus interface selectable using 16/68 pin  
I 1.8 V operation  
I Up to 5 Mbit/s data rate  
I 128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU  
I 128-byte receive FIFO with error flags to reduce the bandwidth requirement of the  
external CPU  
I 128 programmable Receive and Transmit FIFO interrupt trigger levels  
I 128 Receive and Transmit FIFO reporting levels (level counters)  
I Automatic software (Xon/Xoff) and hardware (RTS/CTS or DTR/DSR) flow control  
I Industrial temperature range (40 °C to +85 °C)  
I 128 hardware and software trigger levels  
I Automatic 9-bit mode (RS-485) address detection  
I Automatic RS-485 driver turn-around with programmable delay  
I UART software reset  
I High resolution clock prescaler, from 0 to 15 with granularity of 116 to allow  
non-standard UART clock to be used  
I Programmable Xon/Xoff characters  
 
 

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