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SC16C752BIB48-S

更新时间: 2024-02-29 22:13:26
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恩智浦 - NXP 微控制器和处理器串行IO控制器通信控制器外围集成电路先进先出芯片数据传输时钟
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47页 217K
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SC16C752BIB48-S 数据手册

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SC16C752B  
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with  
64-byte FIFOs  
Rev. 03 — 14 December 2004  
Product data  
1. Description  
The SC16C752B is a dual universal asynchronous receiver/transmitter (UART) with  
64-byte FIFOs, automatic hardware/software flow control, and data rates up to  
5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a  
transmission control register (TCR) that stores receiver FIFO threshold levels to  
start/stop transmission during hardware and software flow control. With the FIFO  
RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one  
access. On-chip status registers provide the user with error indications, operational  
status, and modem interface control. System interrupts may be tailored to meet user  
requirements. An internal loop-back capability allows on-board diagnostics.  
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and  
receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or  
8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be  
programmed to interrupt at different trigger levels. The UART generates its own  
desired baud rate based upon a programmable divisor and its input clock. It can  
transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect  
break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can  
detect FIFO underflow. The UART also contains a software interface for modem  
control operations, and has software flow control and hardware flow control  
capabilities.  
The SC16C752B is available in plastic LQFP48 and HVQFN32 packages.  
2. Features  
Dual channel  
Pin compatible with SC16C2550 with additional enhancements  
Up to 5 Mbit/s baud rate (at 3.3 V and 5 V; at 2.5 V maximum baud rate is  
3 Mbit/s)  
64-byte transmit FIFO  
64-byte receive FIFO with error flags  
Programmable and selectable transmit and receive FIFO trigger levels for DMA  
and interrupt generation  
Software/hardware flow control  
Programmable Xon/Xoff characters  
Programmable auto-RTS and auto-CTS  
Optional data flow resume by Xon any character  
DMA signalling capability for both received and transmitted data  
Supports 5 V, 3.3 V and 2.5 V operation  
5 V tolerant inputs  

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