Datasheet > SA4120APAR-8

SA4120APAR-8

更新时间： 2025-04-25 01:08:31

品牌	Logo	应用领域
SAMES		/
页数	文件大小	规格书
14页	534K
描述
Single Channel Single Phase Bidirectional Energy

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SA4120APAR-8 数据手册

Single Channel Single Phase Bidirectional Energy

Metering IC with Instantaneous Frequency Output

SA4120A

FEATURES



Meets the IEC62053, CBIP-88 and IS137799-1999

specification requirements for Class 1 AC static watt-

hour meters for active energy



Precision on-chip oscillator (70ppm/°C drift)

Precision on-chip voltage reference (10ppm/°C drift)

Integrated anti-creep function

Low power consumption (<20mW typical)

Measures AC inputs only



Pulse output supplies instantaneous active power

information



Bidirectional power and energy measurement

Adaptable to different types of current sensors

Functionally compatible with SA2002H

DESCRIPTION

The SA4120A is an accurate single phase power/energy

metering integrated circuit providing a single chip solution for

single phase energy metering. Very few external components

are required and the SA4120A does not require an external

crystal or voltage reference. A precision oscillator and a

precision voltage reference to supply the circuitry with a

stable frequency and stable reference currents are integrated

on the chip.

instantaneous active power consumption. The pulse output is

intended to interface with a microcontroller or similar pulse

counting circuitry. The SA4120A includes an anti-creep

feature preventing any creep effects in the meter under no-

load conditions.

The SA4120A integrated circuit is available in 8 pin dual inline

(PDIP8) as well as 20 pin and 16 pin small outline (SOIC20,

SOIC16) RoHS compliant package options.

The SA4120A metering integrated circuit generates a pulse

output, the frequency of which is proportional to the

DIGITAL

IIP

SIGNAL PROCESSING

CURRENT

OUTPUT

CHANNEL

ADC

IIN

DIR

Instantaneous

power

PULSE

GENERATION

FOUT

DIGITAL

IVP

VOLTAGE

OUTPUT

CHANNEL

ADC

AGND

POWER ON

RESET

VOLTAGE REFERENCE

AND

OSCILLATOR

AND

VDD

CURRENT BIASING

TIMING

VREF

VSS

Figure 1: Block diagram

*FMO and DIR not available in PDIP8 package type

SPEC-3094 (REV. 2)

29-09-2017

1/14

12 3 4 5 6 7...14

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