Datasheet > S70KL1282GABHV020

S70KL1282GABHV020

更新时间： 2024-11-06 14:56:07

品牌	Logo	应用领域
英飞凌 - INFINEON		/
页数	文件大小	规格书
62页	1210K
描述
128MBit 3.0 V Industrial (105°C) HyperBus HYPERRAM Gen 2.0 in 24 FBGA

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S70KL1282, S70KS1282

128 Mb HYPERRAM™ self-refresh DRAM

(PSRAM)

HYPERBUS™ interface, 1.8 V/3.0 V

Features

• Interface

- HYPERBUS™ interface

- 1.8 V / 3.0 V interface support

• Single-ended clock (CK) - 11 bus signals

• Optional differential clock (CK, CK#) - 12 bus signals

- Chip select (CS#)

- 8-bit data bus (DQ[7:0])

- Hardware reset (RESET#)

- Bidirectional read-write data strobe (RWDS)

• Output at the start of all transactions to indicate refresh latency

• Output during read transactions as read data strobe

• Input during write transactions as write data mask

- Optional DDR center-aligned read strobe (DCARS)

• During read transactions RWDS is offset by a second clock, phase shifted from CK

• The phase shifted clock is used to move the RWDS transition edge within the read data eye

• Performance, power, and packages

- 200 MHz maximum clock rate

- DDR - transfers data on both edges of the clock

- Data throughput up to 400 MBps (3,200 Mbps)

- Configurable burst characteristics

• Linear burst

• Wrapped burst lengths:

16 bytes (8 clocks)

32 bytes (16 clocks)

64 bytes (32 clocks)

128 bytes (64 clocks)

• Hybrid option - one wrapped burst followed by linear burst on 64 Mb. Linear burst across die boundary is

not supported.

- Configurable output drive strength

- Power modes^[1]

• Hybrid sleep mode

• Deep power down

- Array refresh

• Partial memory array(1/8, 1/4, 1/2, and so on)

• Full memory array

- Package

• 24-ball FBGA

Note

1. 128 Mb HYPERRAM™ is a stacked-die chip using the two 64 Mb dice. Only one die at a time can be programmed

to enter hybrid sleep mode or deep power down mode.

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1

002-29416 Rev. *D

2023-05-31

12 3 4 5 6 7...62

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