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S70KL1282GABHM023 PDF预览

S70KL1282GABHM023

更新时间: 2024-11-06 14:56:15
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
50页 1210K
描述
128MBit 3.0 V Automotive (125°C) HyperBus HYPERRAM Gen 2.0 in 24 FBGA

S70KL1282GABHM023 数据手册

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r e s t r i c t e d  
S70KL1282/S70KS1282  
HyperRAM (Self-Refresh DRAM)  
3.0 V/1.8 V, 128-Mbit, Automotive-E (Grade 1)  
Features  
Interface  
• HyperBus Interface  
• 1.8 V / 3.0 V interface support  
- Single-ended clock (CK) - 11 bus signals  
- Optional differential clock (CK, CK#) - 12 bus signals  
• Chip Select (CS#)  
• 8-bit data bus (DQ[7:0])  
• Hardware reset (RESET#)  
• Bidirectional Read-Write Data Strobe (RWDS)  
- Output at the start of all transactions to indicate refresh latency  
- Output during read transactions as Read Data Strobe  
- Input during write transactions as Write Data Mask  
• Optional DDR Center-Aligned Read Strobe (DCARS)  
- During read transactions RWDS is offset by a second clock, phase shifted from CK  
- The Phase Shifted Clock is used to move the RWDS transition edge within the read data eye  
Performance, Power, and Packages  
• 200 MHz maximum clock rate  
• DDR - transfers data on both edges of the clock  
• Data throughput up to 400 MBps (3,200 Mbps)  
• Configurable Burst Characteristics  
- Linear burst  
- Wrapped burst lengths:  
• 16 bytes (eight clocks)  
• 32 bytes (16 clocks)  
• 64 bytes (32 clocks)  
• 128 bytes (64 clocks)  
- Hybrid option - one wrapped burst followed by linear burst on 64 Mb. Linear Burst across die boundary is not  
supported.  
• Configurable output drive strength  
• Power Modes[1]  
- Hybrid Sleep Mode  
- Deep Power Down  
• Array Refresh  
- Partial Memory Array (1/8, 1/4, 1/2, and so on)  
- Full  
• Package  
- 24-ball FBGA  
Preliminary Datasheet  
www.infineon.com  
Please read the Important Notice and Warnings at the end of this document  
page 1 of 50  
002-31333 Rev. *A  
2021-03-22  

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