Target Disconnects .................................................................................................................. 7-92
Target Requested Retries ........................................................................................................ 7-93
Target Aborts ........................................................................................................................... 7-93
PCI Bus Mastership ........................................................................................................................... 7-95
Bus Mastership Latency Components ..................................................................................... 7-95
Bus Arbitration ......................................................................................................................... 7-95
Bus Acquisition ........................................................................................................................ 7-96
Target Latency ......................................................................................................................... 7-96
Target Locking ......................................................................................................................... 7-96
PCI Bus Interrupts............................................................................................................................... 7-98
PCI Bus Parity Errors .......................................................................................................................... 7-98
8. ADD-ON BUS INTERFACE .................................................................................................................... 8-99
Add-On Operation Register Accesses ................................................................................................ 8-99
Add-On Interface Signals ........................................................................................................ 8-99
System Signals ........................................................................................................................ 8-99
Register Access Signals .......................................................................................................... 8-99
Asynchronous Register Accesses ......................................................................................... 8-100
Synchronous FIFO and Pass-Thru Data Register Accesses................................................. 8-100
nv Memory Accesses Through the Add-On General Control/Status Register ....................... 8-100
Mailbox Bus Interface ....................................................................................................................... 8-100
Mailbox Interrupts .................................................................................................................. 8-103
FIFO Bus Interface............................................................................................................................ 8-103
FIFO Direct Access Inputs ..................................................................................................... 8-103
FIFO Status Signals .............................................................................................................. 8-103
FIFO Control Signals ............................................................................................................. 8-103
Pass-Thru Bus Interface ................................................................................................................... 8-103
Pass-Thru Status Indicators .................................................................................................. 8-104
Pass-Thru Control Inputs....................................................................................................... 8-104
Non-Volatile Memory Interface.......................................................................................................... 8-104
Non-Volatile Memory Interface Signals ................................................................................. 8-104
Accessing Non-Volatile Memory ............................................................................................ 8-105
nv Memory Device Timing Requirements .............................................................................. 8-107
9. MAILBOX OVERVIEW ......................................................................................................................... 9-109
Functional Description ...................................................................................................................... 9-109
Mailbox Empty/Full Conditions ...............................................................................................9-110
Mailbox Interrupts ...................................................................................................................9-110
Add-On Outgoing Mailbox 4, Byte 3 Access...........................................................................9-110
Bus Interface ...................................................................................................................................... 9-111
PCI Bus Interface ................................................................................................................... 9-111
Add-On Bus Interface ............................................................................................................. 9-111
8-Bit and 16-Bit Add-On Interfaces ......................................................................................... 9-111
Configuration......................................................................................................................................9-112
Mailbox Status ........................................................................................................................9-112
Mailbox Interrupts ...................................................................................................................9-113
iii
5秒后页面跳转
TLP250光耦合器：资料手册参数分析
DA14580 低功耗蓝牙系统级芯片(SoC)：资料手册参数分析
INA226 高精度电流和功率监控器：资料手册参数分析
SI2302 N沟道MOSFET：资料手册参数分析
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
