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S3028B-1

更新时间： 2024-11-24 19:42:11
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
20页 167K
描述
Transceiver, 1-Func, PQFP64, PLASTIC, QFP-64

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中文翻译

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S3028B-1 技术参数

生命周期：Contact Manufacturer包装说明：QFP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.8JESD-30 代码：S-PQFP-G64
长度：14 mm功能数量：1
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装形状：SQUARE
封装形式：FLATPACK座面最大高度：2.35 mm
标称供电电压：5 V表面贴装：YES
电信集成电路类型：ATM/SONET/SDH TRANSCEIVER温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

S3028B-1 数据手册

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®
Now available with  
Loop Timing!  
DEVICE  
SPECIFICATION  
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER  
S3028  
GENERAL DESCRIPTION  
FEATURES  
• Complies with Bellcore and ITU-T  
specifications  
• Jitter generation better than ITU-T requirements  
• On-chip high-frequency PLL for clock  
generation  
The S3028 SONET/SDH transceiver chip is a fully  
integrated serialization/deserialization SONET  
OC-12 (622.08 Mbit/s) and OC-3 (155.52 Mbit/s) in-  
terface device. The chip performs all necessary  
serial-to-parallel and parallel-to-serial functions in  
conformance with SONET/SDH transmission stan-  
dards. The device is suitable for SONET-based ATM  
applications and can be used in conjunction with  
AMCC’s S3026 Clock Recovery Unit (CRU). Figure  
1 shows a typical network application.  
• Supports 155.52 Mbps (OC-3) and  
622.08 Mbps (OC-12)  
• Selectable reference frequencies of 19.44,  
38.88, 51.84, or 77.76 MHz  
• Interface to both PECL and TTL logic  
• 4-bit or 8-bit OC-3 TTL datapath  
• 8-bit OC-12 TTL datapath  
• Compact 64 PQFP package  
• Diagnostic loopback mode  
• Line loopback mode  
On-chip clock synthesis is performed by the high-  
frequency phase-locked loop on the S3028  
transceiver chip allowing the use of a slower external  
transmit clock reference. The S3028 also performs  
SONET/SDH frame detection. The chip can be used  
with a 19.44, 38.88, 51.84 or 77.76 MHz reference  
clock, in support of existing system clocking  
schemes.  
• Lock detect  
• LOS input  
• Low jitter PECL interface  
• 0.9W typical power dissipation  
• Loop Timing (S3028B only)  
• Forward Clocking (S3028B only)  
• "Squelched Clock" operation (S3028B only)  
• 5 V Power supply  
The low jitter PECL interface guarantees compliance  
with the bit-error rate requirements of the Bellcore  
and ITU-T standards. The S3028 is packaged in a  
64 PQFP, offering designers a small package out-  
line.  
Since the S3028 jitter generation is better than the  
ITU-T requirements over all reference frequencies,  
the designer can meet the overall system require-  
ment including the optical interface devices (refer to  
Table 9 for jitter generation specifications).  
APPLICATIONS  
• SONET/SDH-based transmission systems  
• SONET/SDH modules  
• SONET/SDH test equipment  
• ATM over SONET/SDH  
• Section repeaters  
• Add Drop Multiplexers (ADM)  
• Broad-band cross-connects  
• Fiber optic terminators  
• Fiber optic test equipment  
Figure 1. System Block Diagram  
8
8
S3026  
Transceiver  
S3028  
Fiber  
Optic  
Module  
Fiber  
Optic  
Module  
Transceiver  
S3028  
Controller  
Controller  
8
8
S3026  
December 13, 1999 / Revision H  
1
1234567...20

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