®
DEVICE SPECIFICATION
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
S3005/S3006
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
GENERAL DESCRIPTION
FEATURES
• Complies with ANSI, Bellcore, and ITU-T
specifications
• On-chip high-frequency PLL for clock
generation and clock recovery
The S3005/S3006 Synchronous Electrical Transmit
Interface, SETI, and Synchronous Electrical Receive
Interface, SERI, SONET/SDH and E4 transmitter
and receiver chips are the first fully integrated serial-
ization/deserialization interface devices covering E4
(139.264 Mbit/s), SONET OC-3 (155.52 Mbit/s) and
SONET OC-12 (622.08 Mbit/s). With architecture de-
veloped by PMC-Sierra, the chipset performs all
necessary serial-to-parallel and parallel-to-serial
functions in conformance with SONET/SDH and E4
transmissions standards. Figure 1 shows a typical
network application.
• Supports 139.264 Mbit/s (E4), 155.52 Mbit/s
(OC-3), and 622.08 Mbit/s (OC-12)
transmission rates
• Supports 139.264 Mbit/s and 155.52 Mbit/s
Code Mark Inversion (CMI) interfaces
• Selectable reference frequencies of 19.44,
38.88, 51.84, and 77.76 MHz (OC-3/12) and
17.408, 34.816, 46.421, and 69.632 MHz(E4)
• Interface to both ECL and TTL logic
• 8-bit TTL/CMOS datapath
• Bypass mode for off-chip clocking
• Local and line loopback mode
• Lock detect
• Low jitter ECL interface
• Low power
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3005 SETI
transmitter chip allowing the use of a slower external
transmit clock reference. Clock recovery is per-
formed on the S3006 SERI receiver chip by
synchronizing its on-chip VCO directly to the incom-
ing data stream. The S3006 also performs SONET/
SDH frame detection. The chipset can be used with
19.44, 38.88, 51.84, and 77.76 MHz reference
clocks when operated in the SONET/SDH OC-3 or
OC-12 modes. In the E4 mode the chipset can be
operated with 17.408, 34.816, and 69.632 MHz ref-
erence clocks in support of existing system clocking
schemes. On-chip code-mark-inversion (CMI) encod-
ing and decoding is provided for 139.264 Mbit/s and
155.52 Mbit/s interfaces. If desired, both clock gen-
eration and recovery can be bypassed, allowing the
use of externally generated and recovered clocks.
• 80 PQFP or 68 LDCC package
APPLICATIONS
• SONET/SDH or E4-based transmission systems
• SONET/SDH or E4 modules
• SONET/SDH or E4 test equipment
• ATM over SONET
• Section repeaters
• Add drop multiplexors
• Broadband cross-connects
• Fiber optic terminators
The very low jitter ECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore, ANSI, and ITU-T standards. The S3005/
S3006 SETI and SERI chipset is packaged in a 50
mil pitch, 68-pin LDCC or 25 mil pitch, 80 PQFP
package, offering designers a small package outline.
• Fiber optic test equipment
Figure 1. System Block Diagram
S3005
SONET/SDH
Transmitter
(SETI)
Transmit
Overhead
Processor
8
8
Receive
Overhead
Processor
S3006
SONET/SDH
Receiver
(SERI)
OTX
ORX
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
1