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S29WS128P0LBFW300 PDF预览

S29WS128P0LBFW300

更新时间: 2024-11-07 06:13:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 内存集成电路
页数 文件大小 规格书
91页 996K
描述
Flash, 8MX16, 80ns, PBGA84, FBGA-84

S29WS128P0LBFW300 技术参数

生命周期:Active包装说明:FBGA-84
Reach Compliance Code:compliantECCN代码:3A991.B.1.A
HTS代码:8542.32.00.51风险等级:5.73
最长访问时间:80 ns启动块:BOTTOM/TOP
JESD-30 代码:R-PBGA-B84长度:11.6 mm
内存密度:134217728 bit内存集成电路类型:FLASH
内存宽度:16功能数量:1
端子数量:84字数:8388608 words
字数代码:8000000工作模式:SYNCHRONOUS/ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-25 °C
组织:8MX16封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行:PARALLEL
编程电压:1.8 V座面最大高度:1 mm
最大供电电压 (Vsup):1.95 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM类型:NOR TYPE
宽度:8 mmBase Number Matches:1

S29WS128P0LBFW300 数据手册

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S29WS512P  
S29WS256P  
S29WS128P  
SUPPLEMENT  
512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V,  
Simultaneous Read/Write Flash  
Features  
Single 1.8 V read/program/erase (1.70–1.95 V)  
Hardware (WP#) protection of top and bottom sectors  
Dual boot sector configuration (top and bottom)  
Handshaking by monitoring RDY  
90 nm MirrorBit™ Technology  
Simultaneous Read/Write operation with zero latency  
Random page read access mode of 8 words with 20 ns intra  
Offered Packages  
page access time  
– WS512P/WS256P/WS128P: 84-ball FBGA  
(11.6 mm x 8 mm)  
32 Word / 64 Byte Write Buffer  
Low VCC write inhibit  
Sixteen-bank architecture consisting of  
32/16/8 Mwords for 512/256/128P, respectively  
Persistent and Password methods of Advanced Sector  
Protection  
Four 16 Kword sectors at both top and bottom of memory  
array  
Write operation status bits indicate program and erase  
operation completion  
510/254/126 64Kword sectors (WS512/256/128P)  
Suspend and Resume commands for Program and Erase  
Programmable linear (8/16/32) with or without wrap around  
operations  
and continuous burst read modes  
Unlock Bypass program command to reduce programming  
Secured Silicon Sector region consisting of 128 words each  
time  
for factory and 128 words for customer  
Synchronous or Asynchronous program operation,  
20-year data retention (typical)  
independent of burst control register settings  
Cycling Endurance: 100,000 cycles per sector (typical)  
Command set compatible with JEDEC (42.4) standard  
ACC input pin to reduce factory programming time  
Support for Common Flash Interface (CFI)  
General Description  
The Cypress S29WS512/256/128P are Mirrorbit® Flash products fabricated on 90 nm process technology. These burst mode Flash  
devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate  
data and address pins. These products can operate up to 104 MHz and use a single VCC of 1.7 V to 1.95 V that makes them ideal  
for today’s demanding wireless applications requiring higher density, better performance and lowered power consumption.  
Performance Characteristics  
Read Access Times  
Speed Option (MHz)  
Current Consumption (typical values)  
Continuous Burst Read @ 104 MHz  
104  
103.8  
7.6  
36 mA  
40 mA  
20 mA  
20 µA  
Max. Synch Access Time (tIACC  
)
Simultaneous Operation 104 MHz  
Program  
Max. Synch. Burst Access, ns (tBACC  
)
Max OE# Access Time, ns (tOE  
)
7.6  
Standby Mode  
Max. Asynch. Access Time, ns (tACC  
)
80  
Typical Program & Erase Times  
Single Word Programming  
40 µs  
Effective Write Buffer Programming (VCC) Per  
Word  
9.4 µs  
Effective Write Buffer Programming (VACC) Per  
Word  
6 µs  
Sector Erase (16 Kword Sector)  
Sector Erase (64 Kword Sector)  
350 ms  
600 ms  
Cypress Semiconductor Corporation  
Document Number: 002-01747 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 29, 2017  

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