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S29PL127J70TAW133 PDF预览

S29PL127J70TAW133

更新时间： 2024-02-02 19:17:02
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管
页数 文件大小 规格书
101页 7830K
描述
Flash, 8MX16, 70ns, PDSO56, TSOP-56

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S29PL127J70TAW133 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Transferred零件包装代码：TSOP1
包装说明：20 X 14 MM, LEAD FREE COMPLIANT, MO-142EC, TSOP-56针数：56
Reach Compliance Code：not_compliantECCN代码：3A991.B.1.A
HTS代码：8542.32.00.51风险等级：5.26
最长访问时间：70 ns其他特性：TOP AND BOTTOM BOOT BLOCK
启动块：BOTTOM/TOP命令用户界面：YES
通用闪存接口：YES数据轮询：YES
JESD-30 代码：R-PDSO-G56JESD-609代码：e0
长度：18.4 mm内存密度：134217728 bit
内存集成电路类型：FLASH内存宽度：16
湿度敏感等级：3功能数量：1
部门数/规模：16,254端子数量：56
字数：8388608 words字数代码：8000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-25 °C组织：8MX16
封装主体材料：PLASTIC/EPOXY封装代码：TSOP1
封装等效代码：TSSOP56,.8,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE页面大小：8 words
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
电源：3/3.3 V编程电压：3 V
认证状态：Not Qualified就绪/忙碌：YES
座面最大高度：1.2 mm部门规模：4K,32K
最大待机电流：0.000005 A子类别：Flash Memories
最大压摆率：0.07 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
切换位：YES类型：NOR TYPE
宽度：14 mmBase Number Matches：1

S29PL127J70TAW133 数据手册

 浏览型号S29PL127J70TAW133的Datasheet PDF文件第2页浏览型号S29PL127J70TAW133的Datasheet PDF文件第3页浏览型号S29PL127J70TAW133的Datasheet PDF文件第4页浏览型号S29PL127J70TAW133的Datasheet PDF文件第5页浏览型号S29PL127J70TAW133的Datasheet PDF文件第6页浏览型号S29PL127J70TAW133的Datasheet PDF文件第7页 
S29PL-J  
128-/128-/64-/32-Mbit (8/8/4/2M x 16-Bit)  
3V, Flash with Enhanced VersatileIO™  
Distinctive Characteristics  
– Output voltage generated and input voltages tolerated on  
all control inputs and I/Os is determined by the voltage on  
the VIO pin  
– VIO options at 1.8 V and 3 V I/O for PL127J and PL129J  
devices  
Architectural Advantages  
128-/128-/64-/32-Mbit Page Mode devices  
– Page size of 8 words: Fast page read access from random  
locations within the page  
Single power supply operation  
– 3V VIO for PL064J and PL032J devices  
Secured Silicon Sector region  
– Full Voltage range: 2.7 to 3.6 V read, erase, and program  
operations for battery-powered applications  
Dual Chip Enable inputs (only in PL129J)  
– Two CE# inputs control selection of each half of the  
memory space  
Simultaneous Read/Write Operation  
– Data can be continuously read from one bank while  
executing erase/program functions in another bank  
– Zero latency switching from write to read operations  
FlexBank Architecture (PL127J/PL064J/PL032J)  
– 4 separate banks, with up to two simultaneous operations  
per device  
– Up to 128 words accessible through a command sequence  
– Up to 64 factory-locked words  
– Up to 64 customer-lockable words  
Both top and bottom boot blocks in one device  
Manufactured on 110-nm process technology  
Data Retention: 20 years typical  
Cycling Endurance: 1 million cycles per sector typical  
Performance Characteristics  
High Performance  
– Page access times as fast as 20 ns  
– Random access times as fast as 55 ns  
Power consumption (typical values at 10 MHz)  
– 45 mA active read current  
– Bank A:  
PL127J -16 Mbit (4 Kw 8 and 32 Kw 31)  
PL064J - 8 Mbit (4 Kw 8 and 32 Kw 15)  
PL032J - 4 Mbit (4 Kw 8 and 32 Kw 7)  
– Bank B:  
– 17 mA program/erase current  
– 0.2 A typical standby mode current  
PL127J - 48 Mbit (32 Kw 96)  
PL064J - 24 Mbit (32 Kw 48)  
PL032J - 12 Mbit (32 Kw 24)  
Software Features  
Software command-set compatible with JEDEC 42.4  
standard  
– Bank C:  
PL127J - 48 Mbit (32 Kw 96)  
PL064J - 24 Mbit (32 Kw 48)  
PL032J - 12 Mbit (32 Kw 24)  
– Backward compatible with Am29F, Am29LV, Am29DL, and  
AM29PDL families and MBM29QM/RM, MBM29LV,  
MBM29DL, MBM29PDL families  
– Bank D:  
CFI (Common Flash Interface) compliant  
– Provides device-specific information to the system,  
allowing host software to easily reconfigure for different  
Flash devices  
PL127J -16 Mbit (4 Kw 8 and 32 Kw 31)  
PL064J - 8 Mbit (4 Kw 8 and 32 Kw 15)  
PL032J - 4 Mbit (4 Kw 8 and 32 Kw 7)  
FlexBank Architecture (PL129J)  
– 4 separate banks, with up to two simultaneous operations  
per device  
Erase Suspend / Erase Resume  
– Suspends an erase operation to allow read or program  
operations in other sectors of same bank  
Program Suspend / Program Resume  
– Suspends a program operation to allow read operation  
from sectors other than the one being programmed  
Unlock Bypass Program command  
– CE#1 controlled banks:  
Bank 1A: PL129J - 16-Mbit (4Kw 8 and 32Kw 31)  
Bank 1B: PL129J - 48-Mbit (32Kw 96)  
– CE#2 controlled banks:  
Bank 2A: PL129J - 48-Mbit (32 Kw 96)  
Bank 2B: PL129J - 16-Mbit (4 Kw 8 and 32 Kw 31)  
Enhanced VersatileI/O (VIO) Control  
Reduces overall programming time when issuing multiple  
program command sequences  
Cypress Semiconductor Corporation  
Document Number: 002-00615 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 10, 2016  
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