S29GL512N
S29GL256N
S29GL128N
512, 256, 128 Mbit, 3 V, Page Flash
Featuring 110 nm MirrorBit
This product family has been retired and is not recommended for designs. For new and current designs, S29GL128S, S29GL256S,
and S29GL512T supersede the S29GL128N, S29GL256N, and S29GL512N respectively. These are the factory-recommended
migration paths. Please refer to the S29GL-S and S29GL-T Family data sheets for specifications and ordering information.
Distinctive Characteristics
Package Options
Architectural Advantages
Single Power Supply Operation
– 56-pin TSOP
– 64-ball Fortified BGA
– 3 volt read, erase, and program operations
Enhanced VersatileI/O Control
Software & Hardware Features
Software Features
– All input levels (address, control, and DQ input levels) and outputs
are determined by voltage on VIO input. VIO range is 1.65 to VCC
– Program Suspend and Resume: read other sectors before
programming operation is completed
Manufactured on 110 nm MirrorBit Process Technology
Secured Silicon Sector Region
– Erase Suspend and Resume: read/program other sectors before
an erase operation is completed
– 128-word/256-byte sector for permanent, secure identification
through an 8-word/16-byte random Electronic Serial Number,
accessible through a command sequence
– Data# polling and toggle bits provide status
– Unlock Bypass Program command reduces overall multiple-word
programming time
– May be programmed and locked at the factory or by the customer
Flexible Sector Architecture
– CFI (Common Flash Interface) compliant: allows host system to
identify and accommodate multiple flash devices
– S29GL512N: Five hundred twelve 64 Kword (128 Kbyte) sectors
– S29GL256N: Two hundred fifty-six 64 Kword (128 Kbyte) sectors
– S29GL128N: One hundred twenty-eight 64 Kword (128 Kbyte)
sectors
Hardware Features
– Advanced Sector Protection
– WP#/ACC input accelerates programming time (when high
voltage is applied) for greater throughput during system
production. Protects first or last sector regardless of sector
protection settings
Compatibility with JEDEC Standards
– Provides pinout and software compatibility for single-power supply
flash, and superior inadvertent write protection
100,000 Erase Cycles per sector typical
20-year Data Retention typical
– Hardware reset input (RESET#) resets device
– Ready/Busy# output (RY/BY#) detects program or erase cycle
completion
Performance Characteristics
High Performance
Product Availability Table
– 90 ns access time (S29GL128N, S29GL256N)
– 100 ns (S29GL512N)
Density
Init. Access
110 ns
100 ns
110 ns
100 ns
90 ns
VCC
Full
Availability
Now
– 8-word/16-byte page read buffer
– 25 ns page read times
512 Mb
Full
Now
Full
Now
– 16-word/32-byte write buffer reduces overall programming time for
multiple-word updates
256 Mb
128 Mb
Full
Now
Low Power Consumption (typical values at 3.0 V, 5 MHz)
– 25 mA typical active read current;
Regulated
Full
Now
110 ns
100 ns
90 ns
Now
– 50 mA typical erase/program current
– 1 µA typical standby mode current
Full
Now
Regulated
Now
Cypress Semiconductor Corporation
Document Number: 002-01522 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 08, 2016
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