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S25FL064P0XMFB000 PDF预览

S25FL064P0XMFB000

更新时间: 2024-11-08 14:54:23
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
63页 2245K
描述
Quad SPI Flash

S25FL064P0XMFB000 数据手册

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S25FL064P  
64-Mbit 3.0 V SPI Flash Memory  
This product family has been retired and is not recommended for designs. For new and current designs, S25FL064L supersede  
S25FL064P. These are the factory-recommended migration paths. Please refer to the S25FL-L Family data sheets for specifications  
and ordering information.  
Distinctive Characteristics  
CFI (Common Flash Interface) compliant: allows host system  
Architectural Advantages  
Single power supply operation  
to identify and accommodate multiple flash devices  
Process technology  
– Full voltage range: 2.7 to 3.6V read and write operations  
– Manufactured on 90-nm MirrorBit® process technology  
Package option  
Memory architecture  
– Uniform 64-kB sectors  
– Industry Standard Pinouts  
– 16-pin SO package (300 mils)  
– 8-contact WSON package (6 × 8 mm)  
– 24-ball BGA package (6 × 8 mm), 5 × 5 pin configuration  
– 24-ball BGA package (6 × 8 mm), 6 × 4 pin configuration  
Top or bottom parameter block (Two 64-kB sectors (top  
or bottom) broken down into sixteen 4-kB sub-sectors  
each)  
– 256-byte page size  
– Backward compatible with the S25FL064A device  
Program  
Performance Characteristics  
– Page Program (up to 256 bytes) in 1.5 ms (typical)  
– Program operations are on a page by page basis  
– Accelerated programming mode via 9V W#/ACC pin  
– Quad Page Programming  
Speed  
– Normal READ (Serial): 40 MHz clock rate  
– FAST_READ (Serial): 104 MHz clock rate (maximum)  
– DUAL I/O FAST_READ: 80 MHz clock rate or  
20 MB/s effective data rate  
– QUAD I/O FAST_READ: 80 MHz clock rate or  
40 MB/s effective data rate  
Erase  
– Bulk erase function  
– Sector erase (SE) command (D8h) for 64-kB sectors  
– Sub-sector erase (P4E) command (20h) for 4-kB sectors  
– Sub-sector erase (P8E) command (40h) for 8-kB sectors  
Cycling endurance  
– 100,000 cycles per sector typical  
Data retention  
Power saving standby mode  
– Standby Mode 80 μA (typical)  
– Deep Power-Down Mode 3 μA (typical)  
Memory Protection Features  
– 20 years typical  
Memory protection  
Device ID  
– W#/ACC pin works in conjunction with Status Register Bits  
to protect specified memory areas  
– Status Register Block Protection bits (BP2, BP1, BP0) in  
status register configure parts of memory as read-only  
– JEDEC standard two-byte electronic signature  
– RES command one-byte electronic signature for backward  
compatibility  
One time programmable (OTP) area for permanent, secure  
identification; can be programmed and locked at the factory  
or by the customer  
Software Features  
– SPI Bus Compatible Serial Interface  
Cypress Semiconductor Corporation  
Document Number: 002-00649 Rev. *J  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised May 22, 2017  

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