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S25FL064LABMFA001 PDF预览

S25FL064LABMFA001

更新时间： 2024-09-19 11:10:51
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
161页 1356K
描述
Quad SPI Flash

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中文翻译

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S25FL064LABMFA001 数据手册

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S25FL064L  
64 Mb (8 MB) FL-L flash  
SPI multi-I/O, 3.0 V  
General description  
The FL-L family devices are flash non-volatile memory products using:  
• Floating gate technology  
• 65-nm process lithography  
The FL-L family connects to a host system via a serial peripheral interface (SPI). Traditional SPI single bit serial  
input and output (single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide  
Quad I/O (QIO), and Quad Peripheral Interface (QPI) commands. In addition, there are Double Data Rate (DDR)  
Read commands for QIO and QPI that transfer address and read data on both edges of the clock.  
The architecture features a page programming buffer that allows up to 256 bytes to be programmed in one  
operation and provides individual 4 KB sector, 32 KB half block sector, 64 KB block sector, or entire chip erase.  
By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read  
transfer rate can match or exceed traditional parallel interface, asynchronous, NOR Flash memories, while  
reducing signal count dramatically.  
The FL-L family products offer high densities coupled with the flexibility and fast performance required by a  
variety of mobile or embedded applications. Provides an ideal storage solution for systems with limited space,  
signal connections, and power. These memories offer flexibility and performance well beyond ordinary serial  
flash devices. They are ideal for code shadowing to RAM, executing code directly (XIP), and storing re-program-  
mable data.  
Features  
• Serial peripheral interface (SPI) with multi-I/O  
- Clock polarity and phase modes 0 and 3  
- Double data rate (DDR) option  
- Quad peripheral interface (QPI) option  
- Extended addressing: 24- or 32- bit address options  
- Serial command subset and footprint compatible with S25FL-A, S25FL1-K, S25FL-P, S25FL-S, and S25FS-S SPI  
families  
- Multi I/O command subset and footprint compatible with S25FL-P, S25FL-S and S25FS-S SPI families  
• Read  
- Commands: Normal, Fast, Dual I/O, Quad I/O, DualO, QuadO, DDR Quad I/O  
- Modes: Burst wrap, Continuous (XIP), QPI  
- Serial flash discoverable parameters (SFDP) for configuration information  
• Program architecture  
- 256-bytes page programming buffer  
- Program suspend and resume  
• Erase architecture  
- Uniform 4 KB sector erase  
- Uniform 32 KB half block erase  
- Uniform 64 KB block erase  
- Chip erase  
- Erase suspend and resume  
• 100,000 program-erase cycles, minimum  
• 20 year data retention, minimum  
Datasheet  
www.infineon.com  
Please read the Important Notice and Warnings at the end of this document  
page 1  
002-12878 Rev. *G  
2022-07-21  
1234567...161

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