Datasheet > S19205CBI

S19205CBI

更新时间： 2024-11-11 20:11:19

品牌	Logo	应用领域
AMCC		/
页数	文件大小	规格书
3页	42K
描述
Telecom IC

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S19205CBI 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.68
Base Number Matches：	1

S19205CBI 数据手册

Part Number - S19205CBI

Product Brief Version 1.1 - April 2001

ADVANCED PRODUCT BRIEF

KHATANGA

10 Gigabit Ethernet MAC and PHY / OC-192c POS Framer and Mapper

General Description

Features

• Single STS-192c/STM-64 framer/mapper device to

support 10 Gigabit Ethernet (10GbE) serial WAN,

serial LAN and STS-192c/AU-4-64c POS applica-

tions.

• POS processing includes HDLC framing, payload

scrambling (x⁴³+ 1) and transparency processing.

• 10GbE MAC transmit processing includes frame

assembly, pad insertion, and CRC generation.

• Supports full duplex mapping of Ethernet frames into

a single SONET/SDH STS-192c/AU-4-64c (WIS

functionality) in compliance with IEEE P802.3ae /

D2.0 proposed baseline specification for 10GbE over

the WAN.

• 10GbE MAC receive processing includes Ethernet

framing, CRC checking, and frame size monitoring.

• Supports 802.3x PAUSE flow control.

• Provides counters to support implementation of

RMON, 802.3 MIBs.

• SONET/SDH section/line/path processing compliant

with Telcordia GR-253, ANSI T1.105 and T1.416, and

ITU G.751, G.783 and G.804. Provides a subset of

the full SONET/SDH processing which implements

the P802.3ae / D2.0 defined 10GbE WAN Interface

Sublayer (WIS).

• Provides a 622.08 MHz 16-bit bus interface on the

line side in both the TX and RX directions (SFI-4/

XSBI compliant).

• Provides a 644 MHz 16-bit LVDS interface on the line

side in both TX and RX directions for LAN PHY appli-

cations (XSBI).

• Performs 10GbE MAC processing, compliant with

IEEE P802.3ae / D2.0.

• Provides a 64-bit, 200 MHz FlexBus-4^TMsystem

interface (SPI-4 Phase 1 compliant).

• Performs 64B/66B encoding in the TX direction and

64B/66B decoding in the RX direction when operat-

ing in 10GbE mode.

• Direct Map Mode for mapping of any traffic type in

SONET/SDH STS-192c/AU-4-64c payloads

• A WIS bypass mode is provided, to support 10GbE

serial LAN applications.

• 16-bit synchronous microprocessor interface for con-

figuration, control, and status monitoring.

• Supports external MAC implementations.

• Provides a 622.08 MHz 16-bit line bus to support

Automatic Protection Switching (APS) configurations.

• Alternatively, supports full-duplex mapping of packets

in a single SONET/SDH STS-192c/AU-4-64c per

IETF 2615 (POS).

• Packaged in a 624-pin CBGA.

• Implemented in .18 micron CMOS, 1.8V and 2.5V

technology.

• SONET/SDH processing includes termination and

generation of section, line, & path layers, with trans-

port/section and path overhead interfaces in both

transmit and receive directions.

S19205CBI Block Diagram

TOH INSERT

SYSTEM

MUX

MICROPROCESSOR I/F

INTRFC

Control

10G

MAC

64B66B

Encoder

TX_CLK_OUT

TX_DATA_OUT[15:0]

SPE

GEN

STX_DATA_IN[63:0]

FIFO

Encoder

FRGEN

MUX

FRTX

HDLC

Proc

TOH

MON.

POH

MON

FRMR

HDLC

Proc

LBK

SEL

RX_DATA_IN[15:0]

RX_CLK_IN

SYSTEM

INTRFC

64B66B

SRX_DATA_OUT[63:0]

Control

PTR

INT

Decoder

10G

MAC

JTAG

TOH EXTRACT

LOC

DET

FIFO

FRM

Advanced Information - The information contained in this

document is about a product in its design stage and is subject

to change without notice at any time. All features described

herein are design goals. Contact AMCC for updates to this

document and the latest product status.

AMCC - Confidential and Proprietary

12 3

中文翻译

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