Datasheet
R01DS0261EJ0120
Rev.1.20
RX230 Group, RX231 Group
Renesas MCUs
Sep 28, 2018
54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory,
various communication functions including USB 2.0 full-speed host/function/OTG, CAN, SD host
interface, serial sound interface, capacitive touch sensing unit, 12-bit A/D, 12-bit D/A, RTC, Encryption
functions
Features
■ 32-bit RXv2 CPU core
• Max. operating frequency: 54 MHz
PLQP0100KB-B 14 × 14 mm, 0.5 mm pitch
PLQP0064KB-C 10 × 10 mm, 0.5 mm pitch
PLQP0048KB-B 7 × 7 mm, 0.5 mm pitch
Capable of 88.56 DMIPS in operation at 54 MHz
• Enhanced DSP: 32-bit multiply-accumulate and 16-bit
multiply-subtract instructions supported
• Built-in FPU: 32-bit single-precision floating point (compliant to
IEEE754)
• Divider (fastest instruction execution takes two CPU clock cycles)
• Fast interrupt
PWQN0064KC-A 9 × 9 mm, 0.5 mm pitch
PWQN0048KB-A 7 × 7 mm, 0.5 mm pitch
• CISC Harvard architecture with 5-stage pipeline
• Variable-length instructions, ultra-compact code
• On-chip debugging circuit
PTLG0100KA-A 5.5 × 5.5 mm, 0.5 mm pitch
PWLG0064KA-A 5 × 5 mm, 0.5 mm pitch
• Memory protection unit (MPU) supported
■ Low power design and architecture
• Operation from a single 1.8-V to 5.5-V supply
■ Up to 14 communication functions
• RTC capable of operating on the battery backup power supply
• Three low power consumption modes
• Low power timer (LPT) that operates during the software standby state
• USB 2.0 host/function/On-The-Go (OTG) (one channel),
full-speed = 12 Mbps, low-speed = 1.5 Mbps, isochronous transfer, and
BC (Battery Charger) supported
• CAN (one channel) compliant to ISO11898-1:
■ On-chip flash memory for code
• 128- to 512-Kbyte capacities
Transfer at up to 1 Mbps
• SCI with many useful functions (up to 7 channels)
Asynchronous mode, clock synchronous mode, smart card interface
Reduction of errors in communications using the bit modulation
function
• On-board or off-board user programming
• Programmable at 1.8 V
• For instructions and operands
■ On-chip data flash memory
• 8 Kbytes (1,000,000 program/erase cycles (typ.))
• BGO (Background Operation)
• IrDA interface (one channel, in cooperation with the SCI5)
2
• I C bus interface: Transfer at up to 400 kbps, capable of SMBus
operation (one channel)
• RSPI (one channel): Transfer at up to 16 Mbps
• Serial sound interface (one channel)
• SD host interface (optional: one channel) SD memory/ SDIO 1-bit or
4-bit SD bus supported
■ On-chip SRAM, no wait states
• 32- to 64-Kbyte size capacities
■ Data transfer functions
• DMAC: Incorporates four channels
• DTC: Four transfer modes
■ Up to 20 extended-function timers
• 16-bit MTU: input capture, output compare, complementary PWM
output, phase counting mode (six channels)
• 16-bit TPU: input capture, output compare, phase counting mode (six
channels)
• 8-bit TMR (four channels)
• 16-bit compare-match timers (four channels)
■ ELC
• Module operation can be initiated by event signals without using
interrupts.
• Linked operation between modules is possible while the CPU is sleeping.
■ Reset and supply management
• Eight types of reset, including the power-on reset (POR)
• Low voltage detection (LVD) with voltage settings
■ 12-bit A/D converter
• Capable of conversion within 0.83 μs
• 24 channels
• Sampling time can be set for each channel
• Self-diagnostic function and analog input disconnection detection
assistance function
■ Clock functions
• Main clock oscillator frequency: 1 to 20 MHz
• External clock input frequency: Up to 20 MHz
• Sub-clock oscillator frequency: 32.768 kHz
• PLL circuit input: 4 MHz to 12.5 MHz
■ 12-bit D/A converter
• Two channels
• On-chip low- and high-speed oscillators, dedicated on-chip low-speed
oscillator for the IWDT
• USB-dedicated PLL circuit: 4, 6, 8, or 12 MHz
54 MHz can be set for the system clock and 48 MHz for the USB clock
• Generation of a dedicated 32.768-kHz clock for the RTC
• Clock frequency accuracy measurement circuit (CAC)
■ Capacitive touch sensing unit
• Self-capacitance method: A single pin configures a single key,
supporting up to 24 keys
• Mutual capacitance method: Matrix configuration with 24 pins, supporting
up to 144 keys
■ Realtime clock
■ Analog comparator
• Two channels × two units
■ General I/O ports
• 5-V tolerant, open drain, input pull-up, switching of driving capacity
• Adjustment functions (30 seconds, leap year, and error)
• Calendar count mode or binary count mode selectable
• Time capture function
• Time capture on event-signal input through external pins
■ Independent watchdog timer
• 15-kHz on-chip oscillator produces a dedicated clock signal to drive
IWDT operation.
■ Encryption Functions (TSIP-Lite)
• Unauthorized access to the encryption engine is disabled and
imposture and falsification of information are prevented
• Safe management of keys
■ Useful functions for IEC60730 compliance
• Self-diagnostic and disconnection-detection assistance functions for
the A/D converter, clock frequency accuracy measurement circuit,
independent watchdog timer, RAM test assistance functions using the
DOC, etc.
• 128- or 256-bit key length of AES for ECB, CBC, GCM, others
• True random number generator
■ Temperature sensor
■ Operating temperature range
• −40 to +85°C
• −40 to +105°C
■ External address space
• Four CS areas (4 × 16 Mbytes)
• 8- or 16-bit bus space is selectable per area
■ Applications
• General industrial and consumer equipment
■ MPC
• Input/output functions selectable from multiple pins
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 1 of 170
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