Advance v0.1
®
Radiation-Tolerant ProASIC3 Low-Power Space-
Flight Flash FPGAs
with Flash*Freeze Technology
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Features and Benefits
MIL-STD-883 Class B Qualified Packaging
• Ceramic Column Grid Array with Six Sigma Copper-
Wrapped Lead-Tin Columns
Advanced and Pro (Professional) I/Os
• 700 Mbps DDR, LVDS-Capable I/Os
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage
• Land Grid Array
Operation
Low Power
• Bank-Selectable I/O Voltages—up to 8 Banks per Chip
• Dramatic Reduction in Dynamic and Static Power
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
• 1.2 V to 1.5 V Core and I/O Voltage Support for Low
Power
• Low Power Consumption in Flash*Freeze Mode Enables
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS
Instantaneous Entry To
Flash*Freeze Mode
/
Exit From Low-Power
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II (RT3PE3000L only)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Programmable Input Delay (RT3PE3000L only)
• Supports Single-Voltage System Operation
• Low-Impedance Switches
Radiation Tolerant
• 15 krad Total Ionizing Dose (TID)
• Wafer-Lot-Specific TID Reports
High Capacity
• Schmitt Trigger Option on Single-Ended Inputs
• 600 k to 3 M System Gates
• Up to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
(RT3PE3000L)
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Pin-Compatible Packages across the Radiation-Tolerant
ProASIC®3 Family
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, All with Integrated PLL (RT ProASIC3)
• Configurable Phase Shift, Multiply/Divide, Delay
• Retains Programmed Design when Powered Off
Capabilities, and External Feedback
• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V
systems) and 350 MHz (1.5 V systems)
High Performance
• 350 MHz (1.5 V) and 250 MHz (1.2 V) System Performance
• 3.3 V, 66 MHz, 66-Bit PCI (1.5 V); 66 MHz, 32-Bit PCI (1.2 V)
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4,
×9, and ×18 organizations available)
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Blocks with Synchronous Operation:
– 250 MHz: For 1.2 V Systems
• FlashLock® to Secure FPGA Contents
High-Performance Routing Hierarchy
– 350 MHz: For 1.5 V Systems
• Segmented, Hierarchical Routing and Clock Structure
Table I-1 • Radiation-Tolerant (RT) ProASIC3 Low-Power Space-Flight FPGAs
RT ProASIC3 Devices
System Gates
RT3PE600L
RT3PE3000L
600 k
13,824
108
24
3 M
75,264
504
112
1 k
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
1 k
Yes
6
Yes
6
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals
I/O Banks
18
18
8
8
Maximum User I/Os
270
620
Package Pins
CCGA/LGA
CG/LG484
CG/LG484, CG/LG896
September 2008
I
© 2008 Actel Corporation
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