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RPIXP2400AB PDF预览

RPIXP2400AB

更新时间: 2024-02-11 05:59:10
品牌 Logo 应用领域
英特尔 - INTEL /
页数 文件大小 规格书
126页 2374K
描述
Microprocessor, PBGA1356,

RPIXP2400AB 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:BGA, BGA1356,37X37,40Reach Compliance Code:compliant
风险等级:5.88JESD-30 代码:S-PBGA-B1356
端子数量:1356最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA1356,37X37,40
封装形状:SQUARE封装形式:GRID ARRAY
电源:1.3,1.5,2.5,3.3 V认证状态:Not Qualified
子类别:Microprocessors表面贴装:YES
温度等级:COMMERCIAL端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
Base Number Matches:1

RPIXP2400AB 数据手册

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Intel® IXP2400 Network Processor  
Datasheet  
Product Features  
The Intel® IXP2400 Network Processor enables faster deployment of intelligent  
network services by providing high programming flexibility, code re-use, and  
high-performance processing. IXP2400 Network Processor supports a wide  
variety of WAN and LAN applications requiring support for a broad range of  
speeds, currently ranging from OC-3 to OC-48. High performance and  
scalability is achieved through an innovative Microengine architecture that  
includes a multi-threaded distribution cache architecture that enables pipeline  
features in software. The Microengines feature innovative inter-thread  
communication capabilities for efficient processing at high line rates, and  
general-purpose hardware elements that support advanced networking  
algorithms. The Microengines play a key role in the Intel® Exchange  
Architecture (IXA) store and forward architecture, providing flexible, rich  
network processing in converged communications environments.  
Eight integrated Microengine Version 2  
Industry-standard PCI Bus Version 2.2  
Processors  
interface for 64-bit, 66-MHz I/O  
— Operating frequencies of 400 and 600 MHz  
— Configurable to four or eight threads per  
Microengine  
— 640 x 32-bit local memory per Microengine  
— Sixteen-entry CAM per Microengine with  
single cycle lookup  
— Next Neighbor bus: A dedicated datapath  
between adjacent Microengines  
— CRC unit per Microengine supporting  
CRC-16 (CCITT) and CRC-32  
— 4K-instruction control store per Microengine  
— Support for Generalized Thread Signaling  
— Reflector access to read or write data between  
any Microengines  
Industry-standard double-data-rate (DDR)  
SDRAM memory interface  
— Peak bandwidth of 2.4 GB/s  
— Clock speeds of 100, 150 MHz supported  
when IXP2400 is running at 600 MHz; 100  
MHz when IXP2400 is running at 400 MHz  
— Error correction code (ECC)  
— Addressable from the Intel XScale core, MEs,  
and PCI  
Two industry-standard 32-bit quad-data-rate  
(QDR) SRAM interfaces  
— Peak bandwidth of 1.6 GB/s per channel  
— 100- or 133-MHz SRAM when IXP2400 is  
running at 400 MHz; 100-, 150- or 200-MHz  
SRAM when IXP2400 is running at 600 MHz  
— Hardware support for Linked List and Ring  
operations  
Integrated Intel XScale core  
— Operating frequencies of 400 and 600 MHz  
— High-performance, low-power, 32-bit  
embedded RISC processor  
— Atomic bit operations  
— Atomic arithmetic support  
— Addressable from the Intel XScale core, MEs,  
— 32-Kbyte instruction cache  
— 32-Kbyte data cache  
— 2-Kbyte mini data cache  
and PCI  
Two uni-directional 32-bit low-voltage  
transistor-transistor logic (LVTTL) data  
interfaces  
Additional integrated features  
— Hardware hash unit (48, 64 and 128 bit)  
— 16-Kbyte scratchpad memory  
— Serial port for debug  
— Speeds from 25 to 133 MHz supported  
— Separately configurable for POS-PHY,  
UTOPIA 1/2/3, or CSIX-L1-B Protocol  
support  
— Eight general-purpose I/O pins  
— Four 32-bit timers  
1356-Ball FCBGA2 package  
— Dimensions of 37.5 mm x 37.5 mm  
— 1 mm solder ball pitch  
— Interprocessor “Cbus” communication  
Notice: Please verify with your local Intel sales office that you have the latest datasheet before  
finalizing a design.  
February 2004  
Document Number: 301164-011  

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