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RN2119MFV(TL3PAV) PDF预览

RN2119MFV(TL3PAV)

更新时间: 2024-11-11 20:10:59
品牌 Logo 应用领域
东芝 - TOSHIBA 开关光电二极管晶体管
页数 文件大小 规格书
5页 155K
描述
Small Signal Bipolar Transistor, 0.1A I(C), 50V V(BR)CEO, 1-Element, PNP, Silicon

RN2119MFV(TL3PAV) 技术参数

生命周期:Obsolete包装说明:SMALL OUTLINE, R-PDSO-F3
Reach Compliance Code:unknown风险等级:5.76
最大集电极电流 (IC):0.1 A集电极-发射极最大电压:50 V
配置:SINGLE WITH BUILT-IN RESISTOR最小直流电流增益 (hFE):120
JESD-30 代码:R-PDSO-F3元件数量:1
端子数量:3封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
极性/信道类型:PNP表面贴装:YES
端子形式:FLAT端子位置:DUAL
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

RN2119MFV(TL3PAV) 数据手册

 浏览型号RN2119MFV(TL3PAV)的Datasheet PDF文件第2页浏览型号RN2119MFV(TL3PAV)的Datasheet PDF文件第3页浏览型号RN2119MFV(TL3PAV)的Datasheet PDF文件第4页浏览型号RN2119MFV(TL3PAV)的Datasheet PDF文件第5页 
RN2119MFV  
TOSHIBA Transistor Silicon PNP Epitaxial Type (PCT Process) (Bias Resistor built-in Transistor)  
RN2119MFV  
Switching, Inverter Circuit, Interface Circuit  
and Driver Circuit Applications  
Unit: mm  
z With built-in bias resistors  
1.2±0.05  
z Simplify circuit design  
0.8±0.05  
z Reduce a quantity of parts and manufacturing process  
z Complementary to RN1119MFV  
1
Equivalent Circuit  
2
3
1.BASE  
VESM  
2.EMITTER  
3.COLLECTOR  
Absolute Maximum Ratings (Ta = 25°C)  
JEDEC  
JEITA  
Characteristic  
Collector-base voltage  
Symbol  
Rating  
Unit  
TOSHIBA  
2-1L1A  
V
CBO  
V
CEO  
V
EBO  
50  
50  
V
V
Weight: 1.5 mg (typ.)  
Collector-emitter voltage  
Emitter-base voltage  
5  
V
Collector current  
I
100  
150  
mA  
mW  
°C  
°C  
C
Collector power dissipation  
Junction temperature  
Storage temperature range  
P (Note1)  
C
T
150  
j
T
stg  
55 to 150  
Note:  
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the  
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly  
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute  
maximum ratings.  
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook  
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test  
report and estimated failure rate, etc).  
Note 1: Mounted on FR4 board (25.4 mm × 25.4 mm × 1.6 mmt)  
Land Pattern Sample  
(unit: mm)  
0.5  
0.45  
1.15  
0.4  
0.45  
0.4  
0.4  
Start of commercial production  
2005-09  
1
2014-03-01  

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