Datasheet > RM7935

RM7935

更新时间： 2024-10-30 03:36:31

品牌	Logo	应用领域
PMC		微处理器
页数	文件大小	规格书
2页	210K
描述
64-bit Microprocessors with Integrated L2 Cache and EJTAG

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中文翻译

获取价格

技术参数
数据手册

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RM7935 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.84	Base Number Matches：	1

RM7935 数据手册

RM7935/RM7965

64-bit Microprocessors with Integrated L2 Cache and EJTAG

Released

Product Brief

• High-performance system interface:

PRODUCT HIGHLIGHTS

• New high performance MIPS64-compatible Instruction Set

•

32-bit multiplexed address/data (SysAD) bus with RM7935.

64-bit SysAD with RM7965.

Architecture with integrated L2 cache and EJTAG:

Multiple outstanding reads with out-of-order return.

1600 Mbyte/s peak throughput.

•

668, 750, 835 and 900 MHz operating frequency.

1890 Dhrystone 2.1 MIPS @ 900 MHz.

200 MHz maximum frequency using HSTL signaling on the SysAD

bus.

Dual-issue superscalar 7-stage pipeline.

16 Kbyte, 4-way set associative L1 Instruction cache.

16 Kbyte, 4-way set associative L1 Data cache.

•

SysAD bus supports 1.5 V, 2.5 V, 3.3 V I/O logic.

Processor clock multipliers 2, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8,

8.5, 9, 10, 11, 12, 13, 14, 15, 16, 17.

256 Kbyte, 4-way set associative L2 cache with industry best 5-

cycle access latency.

• Integrated on-chip EJTAG capability.

•

Fast Packet Cache to assists processing of packet data.

8K entry branch prediction table.

• A 64-entry dynamic Trace Buffer for use in real-time trace and

debug.

Fully associative 64-entry TLB with dual pages.

High-performance Floating Point Unit (IEEE 754).

• Two 32-bit virtually-addressed Watch registers.

• Integrated performance counters:

Fixed-point DSP instructions such as Multiply/Add,

Multiply/Subtract, and 3 Operand Multiply.

•

2 independent 32-bit counters.

•

Counts over 30 processor events including miss predicted

branches.

•

Enables full characterization and analysis of application

software.

BLOCK DIAGRAM

On-Chip Debug

64-bit Integer Unit

Dual-Issue Superscalar

64-bit Floating Point Unit

Double/Single IEEE-754

Branch Trace Buffer

Integer Multiplier

Instruction Dispatch

8K Entry Branch History Tbl

Instruction Cache

16 KB, 4-way

Line Lockable

Data Cache

16 KB, 4-way

Line Lockable

Memory Manager

64-Entry, Dual Page

Secondary Cache

256 KB, 4-way

Line Lockable

Interface Unit

System Control

E9000 Core

SysAD

System Interface

Interrupt

Interface

Cache Test

Mode

PLL & Clock

EJTAG/JTAG

Controller

PMC-2030350, Issue 4

中文翻译

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与RM7935相关器件

型号	品牌	获取价格	描述	数据表
RM7965	PMC	获取价格	64-bit Microprocessors with Integrated L2 Cache and EJTAG
RM7965A-900UI	PMC	获取价格	Microprocessor, 64-Bit, 900MHz, CMOS, PBGA256, 27 X 27 MM, 1.62 MM HEIGHT, MO-192BAL-2, CS
RM7N40S4	RECTRON	获取价格	Vdss (V) : 40 V;Id @ 25C (A) : 7.0 A;Total Gate Charge (nQ) typ : 2.1 nQ;Maximum Power Dis
RM7N60	RECTRON	获取价格	Vdss (V) : 600 V;Id @ 25C (A) : 7.0 A;Rds-on (typ) (mOhms) : 1200 mOhms;Total Gate Charge
RM7N600IP	RECTRON	获取价格	Vdss (V) : 600 V;Id @ 25C (A) : 7.0 A;Rds-on (typ) (mOhms) : 500 mOhms;Total Gate Charge (
RM7N600LD	RECTRON	获取价格	Vdss (V) : 600 V;Id @ 25C (A) : 7.0 A;Rds-on (typ) (mOhms) : 500 mOhms;Total Gate Charge (
RM7P40S8	RECTRON	获取价格	Vdss (V) : 40 V;Id @ 25C (A) : 7.0 A;Rds-on (typ) (mOhms) : 25 mOhms;Total Gate Charge (nQ
RM7W2P-1016	WINCHESTER	获取价格	7W2P RIGHT ANGLE D-SUB
RM7W2S-1002	WINCHESTER	获取价格	D Subminiature Connector
RM7W2S-1022	WINCHESTER	获取价格	D Subminiature Connector, 7 Contact(s), Female, Solder Terminal, Receptacle,

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