RM7000A
64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
•
125 MHz max. freq., multiplexed
address/data bus (SysAD)
•
Specialized DSP integer Multiply-
Accumulate instructions
(MAD/MADU), and three-operand
Multiply instruction (MUL)
FEATURES
• Dual-Issue symmetric superscalar
microprocessor
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Supports two outstanding reads with
out-of-order return
•
400MHz max CPU frequency
•
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I and D Test/Break-point (Watch)
registers for emulation and debug
• High-performance floating-point unit
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Capable of issuing two instructions
per clock cycle
•
800 MFLOPS maximum
Performance counter for system
and software tuning and debug
•
IEEE754 compliant single and
double precision floating-point
operations
• Integrated primary and secondary
caches
•
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16KB Instruction, 16KB Data, and
256KB on-chip secondary
• 64-bit MIPS instruction set architecture
PACKAGING
•
Data PREFETCH instruction allows
the processor to overlap cache miss
latency and instruction execution
•
Fully Static 0.18µ CMOS design
with dynamic power down logic
All are 4-way set associative with
32-byte line size
•
304 pin TBGA package, 31x31 mm
Per-line locking in primary and
secondary caches
•
Single-cycle floating-point multiply-
add
Fast Packet Cache™ increases
system efficiency in networking
applications
DEVELOPMENT TOOLS
• Operating Systems:
• Integrated memory management unit
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Fully associative TLB
•
64/48 dual entries map 128/96
pages
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Linux by MontaVista and Red Hat
VxWorks by Wind River Systems
Nucleus by Accelerated Technology
Neutrino by QNX Software Systems
• Integrated external cache controller
•
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Allows up to 8Mbyte of external
cache for applications with large
data sets
•
Variable page size
• Embedded application enhancements
•
Fourteen fully prioritized vectored
interrupts-10 external, 2 internal, 2
software
• Compiler Suites
• High-performance system interface
•
Algorithmics
•
1000 Mbyte per-second peak
throughput
•
Green Hills Software
BLOCK DIAGRAM
64-bit Integer Unit
Dual-Issue Superscalar
System Control
PC Unit
64-bit FP Unit
Double/Single IEEE754
Integer Multiplier
Instr. Dispatch
I-Cache
16KB, 4-way, lockable
MMU
Fully Assoc., 48 or 64 Entry
D-Cache
16KB, 4-way, lockable
System Cache (L2)
256KB, 4-way, lockable
Bus Interface Unit
SysA /D Bus
Int Ctlr
NMI, INT9 – INT0
PMC- 2010739(R2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2001