5秒后页面跳转
RM7000-250S PDF预览

RM7000-250S

更新时间: 2024-09-16 19:54:03
品牌 Logo 应用领域
PMC 外围集成电路
页数 文件大小 规格书
28页 572K
描述
RISC Microprocessor, 64-Bit, 250MHz, CMOS, PBGA304,

RM7000-250S 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.84
位大小:64JESD-30 代码:S-PBGA-B304
JESD-609代码:e0湿度敏感等级:3
端子数量:304封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA304,23X23,50
封装形状:SQUARE封装形式:GRID ARRAY
电源:2.5,3.3 V认证状态:Not Qualified
速度:250 MHz子类别:Microprocessors
表面贴装:YES技术:CMOS
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
uPs/uCs/外围集成电路类型:MICROPROCESSOR, RISCBase Number Matches:1

RM7000-250S 数据手册

 浏览型号RM7000-250S的Datasheet PDF文件第2页浏览型号RM7000-250S的Datasheet PDF文件第3页浏览型号RM7000-250S的Datasheet PDF文件第4页浏览型号RM7000-250S的Datasheet PDF文件第5页浏览型号RM7000-250S的Datasheet PDF文件第6页浏览型号RM7000-250S的Datasheet PDF文件第7页 
RM7000™ Superscalar  
Dual-Issue Microprocessor  
with On-Chip L2 Cache  
FEATURES  
• Dual Issue symmetric superscalar microprocessor with instruc-  
tion prefetch optimized for system level price/performance  
200, 225, 250, 263, 300 MHz operating frequency  
>500 Dhrystone 2.1 MIPS @ 300 MHz  
• MIPS IV Superset Instruction Set Architecture  
Data PREFETCH instruction allows the processor to overlap  
cache miss latency and instruction execution  
Single-cycle floating-point multiply-add  
14.6-14.8 SPECint95, 14.8-17 SPECfp95 @ 300 MHz  
• Integrated memory management unit  
Fully associative joint TLB (shared by I and D translations)  
64/48 dual entries map 128/96 pages  
Variable page size  
• High-performance system interface  
1000 MB per second peak throughput  
125 MHz max. freq., multiplexed address/data  
Supports two outstanding reads with out-of-order return  
Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9  
• Embedded application enhancements  
Specialized DSP integer Multiply-Accumulate instruction,  
(MAD/MADU) and three-operand multiply instruction (MUL/  
MULU)  
• Integrated primary and secondary caches - all are 4-way set  
associative with 32 byte line size  
16KB instruction, 16KB data, 256KB on-chip secondary  
Per line cache locking in primaries and secondary  
I&D Test/Break-point (Watch) registers for emulation &  
debug  
Performance counter for system and software tuning &  
debug  
Fourteen fully prioritized vectored interrupts - 10 external, 2  
internal, 2 software  
• Integrated external cache controller (up to 8M Bytes)  
• High-performance floating-point unit - 600 M FLOPS maximum  
Single cycle repeat rate for common single-precision opera-  
tions and some double-precision operations  
• Fully static CMOS design with dynamic power down logic  
Standby reduced power mode with WAIT instruction  
3.3 watts typical @ 2.5V Int., 3.3V I/O, 200MHz  
Single cycle repeat rate for single-precision combined multi-  
ply-add operations  
Two cycle repeat rate for double-precision multiply and dou-  
ble-precision combined multiply-add operations  
• RM5271 pin compatible, 304 pin SBGA package, 31x31mm  
BLOCK DIAGRAM  
Extenal Cache Controller  
On-chip 256K Byte Secondary Cache, 4-way Set Associative  
Secondary Tags  
Set A  
Secondary Tags  
Set B  
Secondary Tags  
Set C  
Secondary Tags  
Set D  
DTag  
DTLB  
ITag  
ITLB  
Primary Data Cache  
4-way Set Associative  
Primary Instruction Cache  
4-way Set Associative  
A/D Bus  
Pad Bus  
Store Buffer  
Write Buffer  
Read Buffer  
Pad Buffer  
Address Buffer  
Prefetch Buffer  
Instruction Dispatch Unit  
F Pipe Register  
M Pipe Register  
F-Pipe Bus  
M-Pipe Bus  
D Bus  
Floating-Point  
Load/Align  
Joint TLB  
Load Aligner  
DVA  
Coprocessor 0  
Integer Register File  
Floating-Point  
Register File  
M Pipe  
F Pipe  
Adder  
Adder  
Shifter  
System/Memory  
Control  
Packer/Unpacker  
Comparator  
IVA  
StAln/Sh  
Logicals  
Logicals  
PC Incrementer  
Branch PC Adder  
ITLB Virtual  
Floating-Point  
MultAdd, Add, Sub,  
Cvt, Div, Sqrt  
FA Bus  
DTLB Virtual  
PLL/Clocks  
Multiplier Array  
Program Counter  
Int Mult, Div, Madd  
QUANTUM EFFECT DEVICES, INC., 3255-3 SCOTT BLVD., SUITE 200, SANTA CLARA, CA 95054  
1
PHONE  
FAX  
WEB  
408.565.0300  
408.565.0335  
www.qe dinc.com  

与RM7000-250S相关器件

型号 品牌 获取价格 描述 数据表
RM7000-266S PMC

获取价格

RISC Microprocessor, 64-Bit, 266MHz, CMOS, PBGA304,
RM7000A PMC

获取价格

64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
RM7000A? ETC

获取价格

PMC-2002227 RM7000A Microprocessor with On-Chip Secondary Cache Data Sheet [553 kB]
RM7000A-300T PMC

获取价格

RM7000A™ Microprocessor with On-Chip Second
RM7000A-350T PMC

获取价格

RM7000A™ Microprocessor with On-Chip Second
RM7000A-350TI PMC

获取价格

RM7000A™ Microprocessor with On-Chip Second
RM7000A-400T PMC

获取价格

RM7000A™ Microprocessor with On-Chip Second
RM7000B PMC

获取价格

64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
RM7000B? ETC

获取价格

PMC-2010588 RM7000B Microprocessor with On-Chip Secondary Cache Data Sheet [715 kB]
RM7000B-450T PMC

获取价格

Microprocessor,