RM7000™ Superscalar
Dual-Issue Microprocessor
with On-Chip L2 Cache
FEATURES
• Dual Issue symmetric superscalar microprocessor with instruc-
tion prefetch optimized for system level price/performance
— 200, 225, 250, 263, 300 MHz operating frequency
— >500 Dhrystone 2.1 MIPS @ 300 MHz
• MIPS IV Superset Instruction Set Architecture
— Data PREFETCH instruction allows the processor to overlap
cache miss latency and instruction execution
— Single-cycle floating-point multiply-add
— 14.6-14.8 SPECint95, 14.8-17 SPECfp95 @ 300 MHz
• Integrated memory management unit
— Fully associative joint TLB (shared by I and D translations)
— 64/48 dual entries map 128/96 pages
— Variable page size
• High-performance system interface
— 1000 MB per second peak throughput
— 125 MHz max. freq., multiplexed address/data
— Supports two outstanding reads with out-of-order return
— Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
• Embedded application enhancements
— Specialized DSP integer Multiply-Accumulate instruction,
(MAD/MADU) and three-operand multiply instruction (MUL/
MULU)
• Integrated primary and secondary caches - all are 4-way set
associative with 32 byte line size
— 16KB instruction, 16KB data, 256KB on-chip secondary
— Per line cache locking in primaries and secondary
— I&D Test/Break-point (Watch) registers for emulation &
debug
— Performance counter for system and software tuning &
debug
— Fourteen fully prioritized vectored interrupts - 10 external, 2
internal, 2 software
• Integrated external cache controller (up to 8M Bytes)
• High-performance floating-point unit - 600 M FLOPS maximum
— Single cycle repeat rate for common single-precision opera-
tions and some double-precision operations
• Fully static CMOS design with dynamic power down logic
— Standby reduced power mode with WAIT instruction
— 3.3 watts typical @ 2.5V Int., 3.3V I/O, 200MHz
— Single cycle repeat rate for single-precision combined multi-
ply-add operations
— Two cycle repeat rate for double-precision multiply and dou-
ble-precision combined multiply-add operations
• RM5271 pin compatible, 304 pin SBGA package, 31x31mm
BLOCK DIAGRAM
Extenal Cache Controller
On-chip 256K Byte Secondary Cache, 4-way Set Associative
Secondary Tags
Set A
Secondary Tags
Set B
Secondary Tags
Set C
Secondary Tags
Set D
DTag
DTLB
ITag
ITLB
Primary Data Cache
4-way Set Associative
Primary Instruction Cache
4-way Set Associative
A/D Bus
Pad Bus
Store Buffer
Write Buffer
Read Buffer
Pad Buffer
Address Buffer
Prefetch Buffer
Instruction Dispatch Unit
F Pipe Register
M Pipe Register
F-Pipe Bus
M-Pipe Bus
D Bus
Floating-Point
Load/Align
Joint TLB
Load Aligner
DVA
Coprocessor 0
Integer Register File
Floating-Point
Register File
M Pipe
F Pipe
Adder
Adder
Shifter
System/Memory
Control
Packer/Unpacker
Comparator
IVA
StAln/Sh
Logicals
Logicals
PC Incrementer
Branch PC Adder
ITLB Virtual
Floating-Point
MultAdd, Add, Sub,
Cvt, Div, Sqrt
FA Bus
DTLB Virtual
PLL/Clocks
Multiplier Array
Program Counter
Int Mult, Div, Madd
QUANTUM EFFECT DEVICES, INC., 3255-3 SCOTT BLVD., SUITE 200, SANTA CLARA, CA 95054
1
PHONE
FAX
WEB
408.565.0300
408.565.0335
www.qe dinc.com