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RM48L730 PDF预览

RM48L730

更新时间： 2024-09-16 12:21:43
品牌 Logo 应用领域
德州仪器 - TI 闪存微控制器
页数 文件大小 规格书
147页 2764K
描述
RM48Lx30 16/32-Bit RISC Flash Microcontroller

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RM48L930  
RM48L730  
RM48L530  
www.ti.com  
SPNS176–SEPTEMBER 2011  
RM48Lx30 16/32-Bit RISC Flash Microcontroller  
1 RM48Lx30 16/32-Bit RISC Flash Microcontroller  
1.1 Features  
1
• High-Performance Microcontroller for Safety  
• Multiple Communication Interfaces  
– USB  
Critical Applications  
– Dual CPU’s running in lockstep  
– ECC on flash and RAM interfaces  
– Built-In Self Test for CPU and on-chip RAMs  
– Error Signaling Module with Error Pin  
– Voltage and Clock Monitoring  
•
2-port USB Specification, revision  
2.0-compatible host controller, based on  
the OHCI Specification for USB, release  
1.0  
One full-speed USB device compatible  
with the USB Specification, revision 2.0  
and USB Specification, revision 1.1  
•
• ARM® Cortex™ – R4F 32-bit RISC CPU  
– Efficient 1.6DMIPS/MHz with 8-stage pipeline  
– Three CAN Controllers (DCAN)  
– Floating-Point Unit with Single/Double  
•
•
64 mailboxes with parity protection each  
Compliant to CAN protocol version 2.0B  
Precision  
– 12-Region Memory Protection Unit  
– Open Architecture with 3rd Party Support  
• Operating Conditions  
– Inter-Integrated Circuit (I2C)  
– Three Multi-buffered Serial Peripheral  
Interfaces (MibSPI)  
•
– Two Standard Serial Peripheral Interfaces  
– Up to 200MHz System Clock  
128 Words with Parity Protection each  
– Core Supply Voltage (VCC): 1.2V nominal  
– I/O Supply Voltage (VCCIO): 3.3V nominal  
• Integrated Memory  
(SPI)  
– Local Interconnect Network Interface (LIN)  
– Up to 3MB Program Flash with ECC  
– Up to 256KB RAM with ECC  
Controller  
•
Compliant to LIN protocol version 2.1  
– 64KB Flash for emulated EEPROM  
• 16- bit External Memory Interface  
• Common Platform Architecture  
– Standard Serial Communication Interface  
(SCI)  
• Two High-End Timer Modules (N2HET)  
– N2HET1: 32 programmable channels  
– N2HET2: 20 programmable channels  
– Consistent memory map across family  
– Real-Time Interrupt Timer (RTI) OS Timer  
– 96-channel Vectored Interrupt Module (VIM)  
– 2-channel Cyclic Redundancy Checker (CRC)  
• Direct Memory Access (DMA) Controller  
– 16 Channels and 32 Control Packets  
– Parity protection for control packet RAM  
– DMA Accesses Protected by Dedicated MPU  
– 160 Word Instruction RAM with parity  
protection each  
– Each includes Hardware Angle Generator  
– Dedicated Transfer Unit for each N2HET  
(HTU)  
• Two 10/12-bit Multi-Buffered ADC Modules  
– ADC1: 24 channels  
• Frequency-Modulated Phase-Locked-Loop  
– ADC2: 16 channels  
(FMPLL) with Built-In Slip Detector  
– 16 shared channels  
• Separate Non-Modulating PLL  
– 64 result buffers with parity protection each  
• Packages  
• IEEE 1149.1 JTAG, Boundary Scan and ARM  
CoreSight Components  
• JTAG Security Module  
– 144-pin Quad Flatpack (PGE) [Green]  
– 337-Ball Grid Array (ZWT) [Green]  
• Trace and Calibration Capabilities  
– Embedded Trace Macrocell (ETM-R4)  
– Data Modification Module (DMM)  
– RAM Trace Port (RTP)  
– Parameter Overlay Module (POM)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCT PREVIEW information concerns products in the formative  
Copyright © 2011, Texas Instruments Incorporated  
or design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right  
to change or discontinue these products without notice.  
 
 
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