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RM46L850CPGET PDF预览

RM46L850CPGET

更新时间: 2024-11-19 11:08:03
品牌 Logo 应用领域
德州仪器 - TI 时钟控制器微控制器微控制器和处理器外围集成电路装置闪存
页数 文件大小 规格书
172页 2534K
描述
16/32 位 RISC 闪存 MCU,Cortex R4F,EMAC,USB | PGE | 144 | -40 to 105

RM46L850CPGET 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:LQFP-144
Reach Compliance Code:compliantFactory Lead Time:6 weeks
风险等级:5.76具有ADC:YES
地址总线宽度:位大小:32
边界扫描:YESCPU系列:CORTEX-R4F
最大时钟频率:80 MHzDAC 通道:NO
DMA 通道:YES外部数据总线宽度:
格式:FLOATING POINT集成缓存:YES
JESD-30 代码:S-PQFP-G144JESD-609代码:e4
长度:20 mm低功率模式:YES
湿度敏感等级:3DMA 通道数量:16
外部中断装置数量:10I/O 线路数量:64
串行 I/O 数:12端子数量:144
计时器数量:41片上数据RAM宽度:8
片上程序ROM宽度:8最高工作温度:105 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
RAM(字节):196608RAM(字数):192
ROM(单词):1310720ROM可编程性:FLASH
座面最大高度:1.6 mm速度:200 MHz
最大压摆率:455 mA最大供电电压:1.32 V
最小供电电压:1.14 V标称供电电压:1.2 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:20 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLER, RISCBase Number Matches:1

RM46L850CPGET 数据手册

 浏览型号RM46L850CPGET的Datasheet PDF文件第2页浏览型号RM46L850CPGET的Datasheet PDF文件第3页浏览型号RM46L850CPGET的Datasheet PDF文件第4页浏览型号RM46L850CPGET的Datasheet PDF文件第5页浏览型号RM46L850CPGET的Datasheet PDF文件第6页浏览型号RM46L850CPGET的Datasheet PDF文件第7页 
RM46L450  
RM46L850  
www.ti.com  
SPNS184 SEPTEMBER 2012  
RM46Lx50 16/32-Bit RISC Flash Microcontroller  
1 RM46Lx50 16/32-Bit RISC Flash Microcontroller  
1.1 Features  
1
• High-Performance Microcontroller for Safety  
Critical Applications  
• Two High-End Timer Modules (N2HET)  
– N2HET1: 32 programmable channels  
– Dual CPUs running in lockstep  
– ECC on flash and RAM interfaces  
– Built-In Self Test for CPU and on-chip RAMs  
– Error Signaling Module with Error Pin  
– Voltage and Clock Monitoring  
– N2HET2: 18 programmable channels  
– 160 Word Instruction RAM with parity  
protection each  
– Each includes Hardware Angle Generator  
– Dedicated Transfer Units (HTU) on N2HETs  
• Two 10/12-bit Multi-Buffered ADC Modules  
– ADC1: 24 channels  
– ADC2: 16 channels  
– 16 shared channels  
– 64 result buffers with parity protection each  
• Multiple Communication Interfaces  
– 10/100 Mbps Ethernet MAC (EMAC)  
• ARM® Cortex™ – R4F 32-bit RISC CPU  
– 1.66DMIPS/MHz with 8-stage pipeline  
– FPU with Single/Double Precision  
– 12-Region Memory Protection Unit  
– Open Architecture with 3rd Party Support  
• Operating Conditions  
– 200MHz System Clock  
– Core Supply Voltage (VCC): 1.14V - 1.32V  
– I/O Supply Voltage (VCCIO): 3.0V - 3.6V  
• Integrated Memory  
IEEE 802.3 compliant (3.3V-I/O only)  
Supports MII, RMII and MDIO  
– USB (revision 2.0 full-speed)  
– Up to 1.25MB Program Flash with ECC  
– Up to 192KB RAM with ECC  
– 64KB Flash for emulated EEPROM with ECC  
• 16- bit External Memory Interface (EMIF)  
• Common Platform Architecture  
2-port USB Specification, revision 2.0-  
compatible host controller, based on the  
OHCI Specification for USB, release 1.0  
USB device compatible with the USB  
Specification, revision 2.0 and USB  
Specification, revision 1.1  
– Consistent memory map across family  
– Real-Time Interrupt Timer (RTI) OS Timer  
– 128-channel Vectored Interrupt Module (VIM)  
– 2-channel Cyclic Redundancy Checker (CRC)  
• Direct Memory Access (DMA) Controller  
– 16 Channels and 32 Control Packets  
– Parity protection for control packet RAM  
– DMA Accesses Protected by Dedicated MPU  
– Three CAN Controllers (DCAN)  
64 mailboxes with parity protection each  
Compliant to CAN protocol version  
2.0A/B  
– Inter-Integrated Circuit (I2C)  
– Three Multi-buffered Serial Peripheral  
Interfaces (MibSPI)  
128 Words with Parity Protection each  
8 Transfer groups  
• Frequency-Modulated Phase-Locked-Loop  
(FMPLL) with Built-In Slip Detector  
• Separate Non-Modulating PLL  
– Up to two Standard Serial Peripheral  
Interfaces (SPI)  
• IEEE 1149.1 JTAG, Boundary Scan and ARM  
CoreSight Components  
• Advanced JTAG Security Module (AJSM)  
• Trace and Calibration Capabilities  
– Two UART (SCI) interfaces, one with Local  
Interconnect Network Interface (LIN 2.1)  
Support  
• Up to 101 general purpose I/O (GIO) capable  
pins  
– Parameter Overlay Module (POM)  
– 16 dedicated GIO pins with interrupt  
generation capability  
• Packages  
• Enhanced Timing Peripherals for Motor Control  
– 7 Enhanced Pulse Width Modulators (ePWM)  
– 6 Enhanced Capture (eCAP)  
– 144-pin Quad Flatpack (PGE) [Green]  
– 337-Ball Grid Array (ZWT) [Green]  
– 2 Enhanced Quadrature Encoder Pulse  
(eQEP)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCT PREVIEW information concerns products in the formative or design phase of  
development. Characteristic data and other specifications are design goals. Texas  
Instruments reserves the right to change or discontinue these products without notice.  
Copyright © 2012, Texas Instruments Incorporated  
 
 

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