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RM12N100LD PDF预览

RM12N100LD

更新时间: 2024-09-17 18:09:07
品牌 Logo 应用领域
RECTRON
页数 文件大小 规格书
6页 371K
描述
Vdss (V) : 100 V;Id @ 25C (A) : 12.0 A;Total Gate Charge (nQ) typ : 26.2 nQ;Maximum Power Dissipation (W) : 34.7 W;Input Capacitance (Ciss) : 1535 pF;Polarity : N-Channel;Mounting Style : SMD/SMT;Package / Case : TO-252(D-PAK)

RM12N100LD 数据手册

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RM12N100LD  
N-Channel Enhancement Mode Power MOSFET  
Description  
The RM12N100LD uses advanced trench technology and  
design to provide excellent RDS(ON) with low gate charge. It  
can be used in a wide variety of applications.  
General Features  
VDS = 100V,ID =12A  
Schematic diagram  
RDS(ON) < 112mΩ @ VGS=10V  
RDS(ON) < 120mΩ @ VGS=4.5V  
Special process technology for high ESD capability  
High density cell design for ultra low Rdson  
Fully characterized avalanche voltage and current  
Good stability and uniformity with high EAS  
Excellent package for good heat dissipation  
Halogen-free  
P/N suffix V means AEC-Q101 qualified, e.g:RM12N100LDV  
Marking and pin assignment  
Application  
Power switching application  
Hard switched and high frequency circuits  
Uninterruptible power supply  
100% UIS TESTED!  
100% ∆Vds TESTED!  
TO-252 -2Ltop view  
Package Marking and Ordering Information  
Device Marking  
Device  
Device Package  
Reel Size  
Tape width  
Quantity  
12N100  
RM12N100LD  
TO-252-2L  
-
-
-
Absolute Maximum Ratings (TC=25 unless otherwise noted)  
Symbol  
VDS  
Parameter  
Limit  
100  
Unit  
Drain-Source Voltage  
Gate-Source Voltage  
Drain Current-Continuous  
V
V
A
20  
VGS  
12  
7.7  
ID  
ID (100  
)
Drain Current-Continuous(TC=100  
Pulsed Drain Current  
)
A
24  
A
IDM  
W
Maximum Power Dissipation  
Single pulse avalanche energy(Note 5)  
34.7  
PD  
EAS  
256  
mJ  
Operating Junction and Storage Temperature Range  
-55 To 150  
TJ,TSTG  
2019-01/83  
REV:O  

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