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RHRXH162373K1

更新时间: 2024-09-25 12:26:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器锁存器逻辑集成电路
页数 文件大小 规格书
18页 506K
描述
Rad hard low voltage CMOS 16-bit D-type latch (3-state) with 3.6 V tolerant inputs and outputs

RHRXH162373K1 技术参数

是否Rohs认证: 不符合生命周期:Active
零件包装代码:DFP包装说明:DFP, FL48,.4,25
针数:48Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.19Is Samacsys:N
系列:ALVC/VCX/AJESD-30 代码:R-CDFP-F48
JESD-609代码:e0长度:15.75 mm
负载电容(CL):30 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DFP封装等效代码:FL48,.4,25
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5/3.3 V
传播延迟(tpd):5.7 ns认证状态:Not Qualified
座面最大高度:2.72 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):2.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:FLAT
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总剂量:100k Rad(Si) V
宽度:9.65 mmBase Number Matches:1

RHRXH162373K1 数据手册

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54VCXH162373  
Rad hard low voltage CMOS 16-bit D-type latch (3-state)  
with 3.6 V tolerant inputs and outputs  
Features  
1.65 to 3.6 V inputs and outputs  
High speed:  
– t = 3.3 ns (Max.) at V = 3.0 to 3.6 V  
PD  
CC  
– t = 4.5 ns (Max.) at V = 2.3 to 2.7 V  
PD  
CC  
Symmetrical impedance outputs:  
– |I | = I = 12 mA (Min.) at V = 3.0 V  
OH  
OL  
CC  
Flat-48  
– |I | = I = 8 mA (Min.) at V = 2.3 V  
OH  
OL  
CC  
Power down protection on inputs and outputs  
26 Ω serie resistors in outputs  
The upper metallic lid is not electrically connected to any  
pins, nor to the IC die inside the package.  
Operating voltage range:  
– V (Opr) = 1.65 V to 3.6 V  
CC  
Description  
Pin and function compatible with 54 series  
HR162373  
The 54VCXH162373 is a low voltage CMOS 16  
bit d-type latch with 3 state outputs non inverting  
fabricated with sub-micron silicon gate and five-  
layer metal wiring C²MOS technology. It is ideal  
for low power and very high speed 1.65 to 3.6 V  
applications; it can be interfaced to 3.6 V signal  
environment for both inputs and outputs. These  
16 bit D-type latches are bite controlled by two  
latch enable inputs (nLE) and two output enable  
inputs (OE). While the nLE input is held at a high  
level, the nQ outputs will follow the data input  
precisely. When the nLE is taken low, the nQ  
outputs will be in a normal logic state (high or low  
logic level) and while high level the outputs will be  
in a high impedance state. Bus hold on data  
inputs is provided in order to eliminate the need  
for external pull-up or pull-down resistor. The  
device circuits is including 26 Ω series resistance  
in the outputs. These resistors permit to reduce  
line noise in high speed applications. All inputs  
and outputs are equipped with protection circuits  
against static discharge, giving them 2 kV ESD  
immunity and transient excess voltage.  
Bus hold provided on both sides  
Cold spare function  
Latch-up performance exceeds  
300 mA (JESD 17)  
ESD performance:  
– HBM > 2000 V  
(MIL STD 883 method 3015); MM > 200 V  
300 krad Mil1019.6 condition A, (RHA QML  
qualification extension undergone)  
No SEL, no SEUand no SET under 110  
Mev/cm2/mg LET heavy ions irradiation  
QML qualified product  
Device fully compliant with  
DSCC SMD 5962-05211  
100 mV typical input hysteresis  
August 2011  
Doc ID 10653 Rev 7  
1/18  
www.st.com  
18  

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