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RHRXH162373K-01V PDF预览

RHRXH162373K-01V

更新时间： 2024-11-28 02:59:35
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器锁存器逻辑集成电路
页数 文件大小 规格书
17页 509K
描述
Rad hard low voltage CMOS 16-bit D-type latch (3-state) with 3.6V tolerant inputs and outputs

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RHRXH162373K-01V 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：DFP
包装说明：DFP, FL48,.4,25针数：48
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.17Is Samacsys：N
系列：ALVC/VCX/AJESD-30 代码：R-CDFP-F48
JESD-609代码：e0长度：15.75 mm
负载电容（CL）：30 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.008 A位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DFP封装等效代码：FL48,.4,25
封装形状：RECTANGULAR封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3 V
传播延迟（tpd）：5.7 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535 Class V座面最大高度：2.72 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.8 V标称供电电压 (Vsup)：2.3 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：FLAT端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
总剂量：100k Rad(Si) V宽度：9.65 mm
Base Number Matches：1

RHRXH162373K-01V 数据手册

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54VCXH162373  
Rad hard low voltage CMOS 16-bit D-type latch (3-state)  
with 3.6V tolerant inputs and outputs  
Features  
■ 1.65 to 3.6V inputs and outputs  
■ High speed:  
– t = 3.3ns (Max) at V = 3.0 to 3.6V  
PD  
CC  
– t = 4.5ns (Max) at V = 2.3 to 2.7V  
PD  
CC  
■ Symmetrical impedance outputs:  
– |I | = I = 12mA (Min) at V = 3.0V  
Flat-48  
OH  
OL  
CC  
– |I | = I = 8mA (Min) at V = 2.3V  
OH  
OL  
CC  
Description  
■ Power down protection on inputs and outputs  
■ 26Ω serie resistors in outputs  
The 54VCXH162373 is a low voltage CMOS 16  
bit d-type latch with 3 state outputs non inverting  
fabricated with sub-micron silicon gate and five-  
■ Operating voltage range:  
– V (Opr) = 1.65V to 3.6V  
CC  
2
layer metal wiring C MOS technology. It is ideal  
■ Pin and function compatible with 54 SERIES  
for low power and very high speed 1.65 to 3.6V  
applications; it can be interfaced to 3.6V signal  
environment for both inputs and outputs.  
HR162373  
■ Bus hold provided on both sides  
■ Cold spare function  
These 16 bit D-TYPE latches are bite controlled  
by two latch enable inputs (nLE) and two output  
enable inputs (OE).  
■ Latch-up performance exceeds  
300mA (JESD 17)  
■ ESD performance:  
While the nLE input is held at a high level, the nQ  
outputs will follow the data input precisely.  
– HBM > 2000V  
(MIL STD 883 method 3015); MM > 200V  
When the nLE is taken low, the nQ outputs will be  
in a normal logic state (high or low logic level) and  
while high level the outputs will be in a high  
impedance state. Bus hold on data inputs is  
provided in order to eliminate the need for  
external pull-up or pull-down resistor. The device  
circuits is including 26Ω series resistance in the  
outputs. These resistors permit to reduce line  
noise in high speed applications.  
■ 300KRad Mil1019.6 Condition A, (RHA QML  
qualification extension undergone)  
■ No SEL, no SEU under 72 Mev/cm2/mg LET  
heavy ions irradiation  
■ QML qualified product  
■ Device fully compliant with  
DSCC SMD 5962-05211  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
July 2007  
Rev 4  
1/17  
www.st.com  
17  
1234567...17

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