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RHFXH162244K03V PDF预览

RHFXH162244K03V

更新时间: 2024-11-26 12:00:55
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
18页 457K
描述
Low voltage CMOS 16-bit bus buffer (3-state non inverter) with 3.6 V tolerant inputs and outputs

RHFXH162244K03V 技术参数

生命周期:Active包装说明:DFP, FL48,.4,25
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:30 weeks
风险等级:5.69控制类型:ENABLE LOW
JESD-30 代码:R-XDFP-F48负载电容(CL):30 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.012 A
位数:4功能数量:4
端子数量:48最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC
封装代码:DFP封装等效代码:FL48,.4,25
封装形状:RECTANGULAR封装形式:FLATPACK
电源:2.5/3.3 VProp。Delay @ Nom-Sup:5.2 ns
认证状态:Not Qualified筛选级别:38535V;38534K;883S
子类别:Bus Driver/Transceivers表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:FLAT端子节距:0.635 mm
端子位置:DUAL总剂量:300k Rad(Si) V
Base Number Matches:1

RHFXH162244K03V 数据手册

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54VCXH162244  
Low voltage CMOS 16-bit bus buffer (3-state non inverter)  
with 3.6 V tolerant inputs and outputs  
Features  
1.65 to 3.6 V inputs and outputs  
High speed:  
– t = 3.4 ns at V = 3.0 to 3.6 V  
PD  
CC  
– t = 3.8 ns at V = 2.3 to 2.7 V  
PD  
CC  
Power down protection on inputs and outputs  
Symmetrical output impedance:  
Flat-48  
– |I | = I = 12 mA (Min.) at V = 3.0 V  
OH  
OL  
CC  
– |I | = I = 8 mA (Min.) at V = 2.3 V  
OH  
OL  
CC  
The upper metallic lid is not electrically connected to any  
pins, nor to the IC die inside the package.  
26 Ω serie resistors in outputs  
Operating voltage range:  
– V (Opr) = 1.65 V to 3.6 V  
CC  
Description  
Pin and function compatible with 54 series  
H162244  
The 54VCXH162244 is a low voltage CMOS 16  
bit bus buffer (non inverted) fabricated with sub-  
micron silicon gate and five-layer metal wiring  
C²MOS technology. It is ideal for low power and  
very high speed 1.65 to 3.6 V applications; it can  
be interfaced to 3.6 V signal environment for both  
inputs and outputs. Any nG output control  
Bus hold provided on data inputs  
Cold spare function  
Latch-up performance exceeds  
300 mA (JESD 17)  
ESD performance:  
governs four BUS buffers. Output enable input  
(nG) tied together gives full 16-bit operation.  
When nG is low, the outputs are on. When nG is  
high, the output are in high impedance state. This  
device is designed to be used with 3 state  
– HBM > 2000 V  
(Mil Std 883 Method 3015); MM > 200 V  
300 krad Mil1019.6 condition A, (RHA QML  
qualification extension undergone)  
memory address drivers, etc. Bus hold on data  
inputs is provided in order to eliminate the need  
for external pull-up or pull-down resistor. The  
device circuits is including 26 Ω series resistance  
in the outputs. These resistors permit to reduce  
line noise in high speed applications. All inputs  
and outputs are equipped with protection circuits  
against static discharge, giving them 2 kV ESD  
immunity and transient excess voltage.  
No SEL, no SEU and no SET under 110  
Mev/cm2/mg LET heavy ions irradiation  
QML qualified product  
SMD 5962-05210  
100 mV typical input hysteresis  
July 2011  
Doc ID 10652 Rev 9  
1/18  
www.st.com  
18  

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