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X9317TP-2.7 PDF预览

X9317TP-2.7

更新时间: 2024-01-08 01:51:05
品牌 Logo 应用领域
瑞萨 - RENESAS 光电二极管转换器电阻器
页数 文件大小 规格书
14页 702K
描述
100K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 100 POSITIONS, PDIP8, PLASTIC, DIP-8

X9317TP-2.7 技术参数

生命周期:Transferred包装说明:PLASTIC, DIP-8
Reach Compliance Code:unknown风险等级:5.82
其他特性:NONVOLATILE MEMORY控制接口:INCREMENT/DECREMENT
转换器类型:DIGITAL POTENTIOMETERJESD-30 代码:R-PDIP-T8
长度:10.03 mm功能数量:1
位置数:100端子数量:8
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
认证状态:Not Qualified电阻定律:LINEAR
最大电阻容差:20%最大电阻器端电压:5 V
最小电阻器端电压:座面最大高度:4.32 mm
标称供电电压:5 V表面贴装:NO
标称温度系数:300 ppm/ °C温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL标称总电阻:100000 Ω
宽度:7.62 mm

X9317TP-2.7 数据手册

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DATASHEET  
X9317  
FN8183  
Rev.10.00  
Dec 17, 2018  
Low Noise, Low Power, 100 Taps, Digitally Controlled Potentiometer (XDCP™)  
The X9317 is a digitally controlled potentiometer (XDCP™). The  
Features  
device consists of a resistor array, wiper switches, a control  
section, and nonvolatile memory. The wiper position is  
controlled by a 3-wire interface.  
• Solid-state potentiometer  
• 3-wire serial up/down interface  
• 100 wiper tap points  
The potentiometer is implemented by a resistor array  
composed of 99 resistive elements and a wiper switching  
network. Between each element and at either end are tap  
points accessible to the wiper terminal. The position of the  
wiper element is controlled by the CS, U/D, and INC inputs. The  
position of the wiper can be stored in nonvolatile memory and  
then be recalled upon a subsequent power-up operation.  
- Wiper position stored in nonvolatile memory and recalled  
on power-up  
• 99 resistive elements  
- Temperature compensated  
- End-to-end resistance range ±20%  
The device can be used as a three-terminal potentiometer for  
voltage control or as a two-terminal variable resistor for current  
control in a wide variety of applications.  
• Low power CMOS  
- V = 2.7V to 5.5V, and 5V ±10%  
CC  
- Standby current <5µA  
Applications  
• LCD bias control  
• High reliability  
- Endurance, 100,000 data changes per bit  
- Register data retention, 100 years  
• DC bias adjustment  
• R  
TOTAL  
values = 10kΩ, 50kΩ, 100kΩ  
• Gain and offset trim  
• Laser diode bias control  
• Voltage regulator output control  
• Packages  
- 8 Ld SOIC, TSSOP, and MSOP  
• Pb-free (RoHS compliant)  
U/D  
INC  
R
99  
H
UP/DOWN  
COUNTER  
V
(SUPPLY VOLTAGE)  
CC  
CS  
98  
97  
96  
R
R
UP/DOWN  
(U/D)  
H
7-BIT  
NONVOLATILE  
MEMORY  
ONE  
OF  
ONE  
CONTROL  
AND  
MEMORY  
INCREMENT  
(INC)  
W
WIPER  
SWITCHES  
RESISTOR  
ARRAY  
HUNDRED  
DECODER  
DEVICE SELECT  
(CS)  
R
L
2
STORE AND  
RECALL  
CONTROL  
CIRCUITRY  
V
(GROUND)  
1
0
SS  
V
CC  
SS  
V
GENERAL  
R
R
L
W
DETAILED  
FIGURE 1. BLOCK DIAGRAM  
FN8183 Rev.10.00  
Dec 17, 2018  
Page 1 of 14  

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