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RD48F4444LVYBB0 PDF预览

RD48F4444LVYBB0

更新时间: 2024-01-03 18:23:46
品牌 Logo 应用领域
英特尔 - INTEL /
页数 文件大小 规格书
58页 1219K
描述
Flash, 64MX16, 85ns, PBGA103, 11 X 11 MM, 1.40 MM HEIGHT, SCSP-103

RD48F4444LVYBB0 数据手册

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Intel StrataFlashWireless Memory  
System (LV18 SCSP)  
1024-Mbit LVX Family with LPSDRAM  
Datasheet  
Product Features  
Device Memory Architecture  
Code Segment Flash Read Performance  
85 ns initial access  
Flash die density: 128-, 256-Mbit  
LPSDRAM die density: 128-, 256-Mbit  
25 ns Asynchronous Page read  
Top or Bottom parameter flash  
configuration  
14 ns Synchronous read (tCHQV  
54 MHz (max.) CLK  
)
Device Voltage  
Data Segment Flash Performance  
170 ns initial access  
Core: VCC = 1.8 V (typ.)  
I/O: VCCQ = 1.8 V (typ.)  
55 ns Asynchronous Page read  
Code Segment Flash Architecture  
Hardware Read-While-Write/Erase  
Multiple 8-Mbit / 16-Mbit partition sizes  
Device Common Performance  
Buffered EFP: 5µs / Byte (typ.) per die  
Buffer Program: 7µs / Byte (typ.) per die  
Concurrent Buffered EFP:  
2-Kbit One-Time-Programmable  
Protection Register  
6.4-Mbps effective with 4 flash dies  
Device Common Architecture  
Data Segment Flash Architecture  
Software Read-While-Write/Erase  
Single partition size die  
Asymmetrical blocking structure  
16-KWord parameter blocks (Top or  
Bottom); 64-KWord main blocks  
Flash Software  
Zero-latency block locking  
IntelFDI, IntelPSM, and Intel  
VFM  
Absolute write protection with block  
lock down using F-VPP and F-WP#  
Common Flash Interface  
Device Packaging  
Basic/Extended Command Set  
103 active balls; 9 x 12 ball matrix  
Area: 9 x 11 mm to 11 x 11 mm  
Height: 1.4 mm  
Quality and Reliability  
Extended temperature: 25 °C to +85 °C  
Minimum 100 K flash block erase cycle  
0.13 µm ETOXVIII flash technology  
SDRAM Architecture and Performance  
Clock rate: 105 MHz  
Four internal banks  
Burst Length: 1, 2, 4, 8, or full page  
Intel StrataFlash® Wireless Memory System (LV18 SCSP) with Low-Power SDRAM (LVX  
family) offers a variety of high performance code segment, large embedded data segment, and  
low-power SDRAM combinations in a common package on 0.13 µm ETOX™ VIII flash  
technology. The LVX family integrates up to two code segment flash dies, two data segment flash  
dies, and two low-power SDRAM dies or one SRAM die in a common x16D Performance ballout.  
Notice: This document contains information on new products in production. The specifications  
are subject to change without notice. Verify with your local Intel sales office that you have the  
latest datasheet before finalizing a design.  
300945-006  
October 2004  

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