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RD48F4044LVZTQ0 PDF预览

RD48F4044LVZTQ0

更新时间: 2024-01-26 07:45:00
品牌 Logo 应用领域
恒忆 - NUMONYX 内存集成电路
页数 文件大小 规格书
112页 1185K
描述
Flash, 48MX16, 88ns, PBGA88, 8 X 11 MM, 1.40 MM HEIGHT, SCSP-88

RD48F4044LVZTQ0 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:8 X 11 MM, 1.40 MM HEIGHT, SCSP-88针数:88
Reach Compliance Code:unknownECCN代码:3A991.B.1.A
HTS代码:8542.32.00.51风险等级:5.57
最长访问时间:88 ns其他特性:SYNCHRONOUS BURST MODE OPERATION ALSO POSSIBLE
启动块:TOPJESD-30 代码:R-PBGA-B88
长度:11 mm内存密度:805306368 bit
内存集成电路类型:FLASH内存宽度:16
功能数量:1端子数量:88
字数:50331648 words字数代码:48000000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-25 °C组织:48MX16
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):240
编程电压:1.8 V认证状态:Not Qualified
座面最大高度:1.4 mm最大供电电压 (Vsup):2 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30类型:NOR TYPE
宽度:8 mmBase Number Matches:1

RD48F4044LVZTQ0 数据手册

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Intel StrataFlash Wireless Memory  
System (LV18/LV30 SCSP)  
1024-Mbit LV Family  
Datasheet  
Product Features  
Device Architecture  
Code Segment Flash Performance  
85 ns initial access at 1.8 V I/O  
25 ns async page read at 1.8 V I/O  
14 ns sync read (tCHQV) at 1.8 V I/O  
54 MHz CLK at 1.8 V I/O  
Flash die density: 128-, 256-Mbit  
Top or Bottom flash parameter  
configuration  
Device Voltage  
Core: VCC = 1.8 V (Typ)  
Data Segment Flash Performance  
170 ns initial access at 1.8 V I/O  
55 ns async page read at 1.8 V I/O  
Code Segment Flash Architecture  
Hardware Read-While-Write/Erase  
Multiple 8-Mbit or 16-Mbit Partition Sizes  
I/O: VCCQ = 1.8 V or 3.0 V (Typ)  
Device Common Performance  
Buffered EFP: 5 µs / Byte (Typ) per die  
Buffer Program: 7 µs / Byte (Typ) per  
die  
Concurrent Buffered EFP: 6.4 Mbits  
per second (4 dies)  
2-Kbit One-Time Programmable (OTP)  
protection register  
Device Common Architecture  
Data Segment Flash Architecture  
Software Read-While-Write/Erase  
Single Partition Size Die  
Asymmetrical blocking structure  
16-KWord parameter blocks (Top or  
Bottom); 64-KWord main blocks  
Flash Software  
Zero-latency block locking  
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Intel FDI, Intel PSM, and Intel VFM  
Common Flash Interface (CFI)  
Absolute write protection with block  
lock down using F-WP#  
Basic/Extended Command Set  
Device Packaging  
Quality and Reliability  
88 balls (8 x 10 active ball matrix) for  
LVQ device and 103 balls (9 x 12 ball  
matrix) for LVX device  
Extended Temp: 25 °C to +85 °C  
Minimum 100 K flash block erase cycle  
0.13 µm ETOX¥ VIII flash technology  
Area: 8 x 11 mm to 11 x 11 mm  
Height: 1.2 mm to 1.4 mm  
The Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP) family offers a variety of  
high performance code segment and large embedded data segment combination flash dies in  
common package footprints and ballouts on 0.13 µm ETOX™ VIII flash technology. The code  
segment flash features 1.8 V low-power operations with flexible multi-partitions, dual operation  
Read-While-Write/Erase, asynchronous and synchronous reads at 54 MHz. The data segment flash  
features 1.8 V low-power operations optimized for cost sensitive large embedded asynchronous  
data application. The LV device integrates up to two code segment flash dies and two data segment  
flash dies compatible with other LQ/LVQ or LX/LVX SCSP family ballout packages.  
Notice: This document contains preliminary information on new products in production. The  
specifications are subject to change without notice. Verify with your local Intel sales office that  
you have the latest datasheet before finalizing a design.  
253854-003  
February 2004  

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