Datasheet > RD48F4040LVZBQ0

RD48F4040LVZBQ0

更新时间： 2024-11-15 10:29:47

品牌	Logo	应用领域
恒忆 - NUMONYX		/
页数	文件大小	规格书
112页	1185K
描述
Flash, 32MX16, 88ns, PBGA88, 8 X 11 MM, 1.20 MM HEIGHT, SCSP-88

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RD48F4040LVZBQ0 数据手册

Intel StrataFlash Wireless Memory

System (LV18/LV30 SCSP)

1024-Mbit LV Family

Datasheet

Product Features

■ Device Architecture

■ Code Segment Flash Performance

—85 ns initial access at 1.8 V I/O

—25 ns async page read at 1.8 V I/O

—14 ns sync read (t_CHQV) at 1.8 V I/O

—54 MHz CLK at 1.8 V I/O

—Flash die density: 128-, 256-Mbit

—Top or Bottom flash parameter

configuration

■ Device Voltage

—Core: V_CC= 1.8 V (Typ)

■ Data Segment Flash Performance

—170 ns initial access at 1.8 V I/O

—55 ns async page read at 1.8 V I/O

■ Code Segment Flash Architecture

—Hardware Read-While-Write/Erase

—Multiple 8-Mbit or 16-Mbit Partition Sizes

—I/O: V_CCQ= 1.8 V or 3.0 V (Typ)

■ Device Common Performance

—Buffered EFP: 5 µs / Byte (Typ) per die

—Buffer Program: 7 µs / Byte (Typ) per

die

—Concurrent Buffered EFP: 6.4 Mbits

per second (4 dies)

—2-Kbit One-Time Programmable (OTP)

protection register

■ Device Common Architecture

■ Data Segment Flash Architecture

—Software Read-While-Write/Erase

—Single Partition Size Die

—Asymmetrical blocking structure

—16-KWord parameter blocks (Top or

Bottom); 64-KWord main blocks

■ Flash Software

—Zero-latency block locking

—Intel FDI, Intel PSM, and Intel VFM

—Common Flash Interface (CFI)

—Absolute write protection with block

lock down using F-WP#

—Basic/Extended Command Set

■ Device Packaging

■ Quality and Reliability

—88 balls (8 x 10 active ball matrix) for

LVQ device and 103 balls (9 x 12 ball

matrix) for LVX device

—Extended Temp: –25 °C to +85 °C

—Minimum 100 K flash block erase cycle

—0.13 µm ETOX¥ VIII flash technology

—Area: 8 x 11 mm to 11 x 11 mm

—Height: 1.2 mm to 1.4 mm

The Intel StrataFlash^®Wireless Memory System (LV18/LV30 SCSP) family offers a variety of

high performance code segment and large embedded data segment combination flash dies in

common package footprints and ballouts on 0.13 µm ETOX™ VIII flash technology. The code

segment flash features 1.8 V low-power operations with flexible multi-partitions, dual operation

Read-While-Write/Erase, asynchronous and synchronous reads at 54 MHz. The data segment flash

features 1.8 V low-power operations optimized for cost sensitive large embedded asynchronous

data application. The LV device integrates up to two code segment flash dies and two data segment

flash dies compatible with other LQ/LVQ or LX/LVX SCSP family ballout packages.

Notice: This document contains preliminary information on new products in production. The

specifications are subject to change without notice. Verify with your local Intel sales office that

you have the latest datasheet before finalizing a design.

253854-003

February 2004

12 3 4 5 6 7...112

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与RD48F4040LVZBQ0相关器件

型号	品牌	获取价格	描述	数据表
RD48F4044LVYBQ0	NUMONYX	获取价格	Flash, 48MX16, 88ns, PBGA88, 8 X 11 MM, 1.40 MM HEIGHT, SCSP-88
RD48F4044LVZTQ0	NUMONYX	获取价格	Flash, 48MX16, 88ns, PBGA88, 8 X 11 MM, 1.40 MM HEIGHT, SCSP-88
RD48F4400L0YDQ0	NUMONYX	获取价格	Flash Memory,
RD48F4400P0TBQ0A	MICRON	获取价格	64Mb, 128Mb, 256Mb, 512Mb, Multilevel Cell, Parallel NOR Flash Memory
RD48F4400P0VBQ	MICRON	获取价格	Micron Parallel NOR Flash Embedded Memory (P30-65nm)
RD48F4400P0VBQ0	INTEL	获取价格	Intel StrataFlash Embedded Memory
RD48F4400P0VBQ0	NUMONYX	获取价格	Numonyx StrataFlash Embedded Memory
RD48F4400P0VBQ0A	MICRON	获取价格	64Mb, 128Mb, 256Mb, 512Mb, Multilevel Cell, Parallel NOR Flash Memory
RD48F4400P0VBQ0B	MICRON	获取价格	64Mb, 128Mb, 256Mb, 512Mb, Multilevel Cell, Parallel NOR Flash Memory
RD48F4400P0VBQE	MICRON	获取价格	Micron Parallel NOR Flash Embedded Memory (P30-65nm)

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