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RD1142

更新时间： 2024-11-06 14:57:51

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莱迪思 - LATTICE		/
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SPI Slave Controller - Documentation

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RD1142 数据手册

SPI Slave Controller

October 2012

Reference Design RD1142

Introduction

The Serial Peripheral Interface (SPI) is used primarily for synchronous serial communication between a host pro-

cessor and its peripherals. The SPI bus is often selected because of its low pin count and full-duplex mode that can

achieve data throughput in the tens of Mbps range. The SPI bus uses a 4-wire interface with two unidirectional data

lines to communicate between the master and the selected slave. It supports one master with multiple slaves on

one bus and allows protocol flexibility for the bit transferred.

This reference design implements a SPI slave device interface that provides full-duplex, synchronous, serial com-

munication with the SPI master. The data size of the SPI bus can be configured to either 16 or 8 bits. The SPI Slave

Controller reference design supports all modes of CPOL and CPHA – 00, 01, 10 and 11.

This design uses three pins (clock, data in and data out) plus one select for each slave device. A SPI is a good

choice for communicating with low-speed devices that are accessed intermittently and transfer data streams rather

than reading and writing to specific addresses. A SPI is an especially good choice if we can take advantage of its

full-duplex capability for sending and receiving data at the same time.

This design is implemented in VHDL. The Lattice iCECube2™ Place and Route tool integrated with Synplify Pro

synthesis tool is used for the implementation of the design. The design uses an iCE40™ ultra low density FPGA

and can be targeted to other iCE40 family members.

Figure 1. Block Diagram

i_sys_rst

i_sys_clk

i_csn

i_wr

i_mosi

i_rd

i_cpol

i_cpha

i_lsb_first

o_miso

i_ssn

Processor

Interface

SPI Bus

SPI Master

SPI Slave

Processor

i_data [15:0]

o_data [15:0]

i_sclk

o_tx_ready

o_rx_ready

o_rx_error

o_tx_error

o_tx_ack

o_tx_no_ack

Features

• Supports all four modes of CPOL and CPHA operation (00/01/10/11)

• Supports variable data widths (8 and 16 bits)

• Provision for easy integration of any processor interface

• IP-XACT version 1.2 compliant

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

rd1142_01.0

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