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RD1101

更新时间： 2024-09-27 14:58:23

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
11页	2508K
描述
I2S Controller with WISHBONE Interface Reference Design Documentation

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RD1101 数据手册

I²S Controller with

WISHBONE Interface

March 2014

Reference Design RD1101

Introduction

The I²S bus (Inter-IC Sound bus) is a 3-wire, half-duplex serial link for connecting digital audio devices in an elec-

tronic system. The bus handles audio data and clocks separately to minimize jitter that may cause data distortion in

the digital analog system. Invented by Philips Semiconductor, the I²S bus is widely used by equipment and IC man-

ufacturers.

This reference design implements an I²S transmit master or I²S receive master with a WISHBONE interface.

Features

The following are some key characteristics of this design:

• Configurable as an I²S transmit master or I²S receive master

• WISHBONE interface

• Configurable sample data resolution from 16 to 32 bits

• Configurable data width from 16 to 32 bits

• Configurable data buffer from 16 to 256 words deep

• Active high interrupt output

Functional Description

This design is configurable via the parameter IS_RECEIVER. When IS_RECEIVER is set to ‘1’, it is configured as

an I²S transmit master; otherwise, it is configured as an I²S receive master. Figure 1 shows the design used as an

I²S transmit master in an I²S system. Figure 2 shows the design used as an I²S receive master in an I²S system.

Figure 1. I²S Transmit Master Connecting to Peripherals

FPGA

sck

I²S Transmitter

Master

Microprocessor

I²S Receiver

Figure 2. I²S Receive Master Connecting to Peripherals

FPGA

sck

I²S Receiver

Master

Microprocessor

I²S Transmitter

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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