Datasheet > RD1044

RD1044

更新时间： 2024-11-10 14:57:51

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
12页	959K
描述
SPI WISHBONE Controller - Documentation

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

RD1044 数据手册

SPI WISHBONE Controller

March 2014

Reference Design RD1044

Introduction

The Serial Peripheral Interface (SPI) bus provides an industry standard interface between microprocessors and

other devices as shown in Figure 1. This reference design documents a SPI WISHBONE controller designed to

provide an interface between a microprocessor with a WISHBONE bus and external SPI devices. In master mode,

the SPI controller can be configured for communication with multiple off-chip SPI ports. In slave mode, the SPI sup-

ports communications with an off-chip SPI master.

As a simple serial port, the SPI uses few FPGA resources (see Table 6) and little board space for wires. This SPI

reference design uses only three pins (clock, data in, and data out) plus one select for each slave device. A SPI is

a good choice for communicating with low-speed devices that are accessed intermittently and transfer data

streams rather than reading and writing to specific addresses. A SPI is an especially good choice if you can take

advantage of its full-duplex nature, which sends and receives data at the same time.

Figure 1. Using the SPI WISHBONE Controller to Connect to Peripherals

Peripheral

FPGA

Slave

SPI

WISHBONE

Controller

Microprocessor

(Master Mode)

Peripheral

Slave

SPI

Both Verilog and VHDL versions of the reference design are available. Lattice design tools are used for synthesis,

place and route and simulation. The design can be targeted to multiple Lattice device families. Its small size makes

it portable across different FPGA or CPLD architectures.

This design assumes the user has experience with WISHBONE controllers. Information available in the documents

listed in the References section is not repeated in this document.

Theory of Operation

Overview

This SPI WISHBONE controller provides an interface between a microprocessor with a WISHBONE bus and a SPI

device. The controller can either act as the SPI Master or SPI Slave device. The selection of the Master or Slave

mode is done using parameters in the HDL code. The design uses a single module.

The SPI WISHBONE reference design provides standard, fully-configurable SPI ports including:

• WISHBONE B.3 interface

• Slave and master modes. Master mode can control up to eight slaves. More can be added if desired.

• Interrupt request to the processor, configurable for a variety of status conditions.

• Configurable serial clock (SCLK) frequency.

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

rd1044_01.7

12 3 4 5 6 7...12

中文翻译

下载PDF

与RD1044相关器件

型号	品牌	获取价格	描述	数据表
RD1046	LATTICE	获取价格	I2C Master with WISHBONE Bus Interface - Documentation
RD1-0502S10A1	RSG	获取价格	DC/DC-Converter
RD1-0502S10A3	RSG	获取价格	DC/DC-Converter
RD1-0503D10AX	RSG	获取价格	DC/DC-Converter
RD1-0503S02AX	RSG	获取价格	DC/DC-Converter
RD1-0503S05A1	RSG	获取价格	DC/DC-Converter
RD1-0503S05A3	RSG	获取价格	DC/DC-Converter
RD1-0503S05AX	RSG	获取价格	DC/DC-Converter
RD1-0503S10A1	RSG	获取价格	DC/DC-Converter
RD1-0503S10A3	RSG	获取价格	DC/DC-Converter

与RD1044相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

22
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

21
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

47
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

39

产品中心

服务支持

精选活动

关于我们

帮助中心

RD1044

RD1044 数据手册

与RD1044相关器件

与RD1044相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

RD1044

RD1044 数据手册

与RD1044相关器件

与RD1044相关文章

您还可以找

您在本页遇到什么问题？