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RC82540EM PDF预览

RC82540EM

更新时间: 2024-02-13 00:42:19
品牌 Logo 应用领域
英特尔 - INTEL 时钟局域网数据传输外围集成电路
页数 文件大小 规格书
44页 257K
描述
LAN Controller, 4 Channel(s), 125MBps, CMOS, PBGA196, 15 X 15 MM, BGA-196

RC82540EM 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:15 X 15 MM, BGA-196针数:196
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.81地址总线宽度:32
边界扫描:NO最大时钟频率:25 MHz
最大数据传输速率:125 MBps外部数据总线宽度:32
JESD-30 代码:S-PBGA-B196JESD-609代码:e0
长度:15 mm串行 I/O 数:4
端子数量:196最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装等效代码:BGA196,14X14,40
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
峰值回流温度(摄氏度):240电源:1.5,2.5,3.3 V
认证状态:Not Qualified座面最大高度:1.5 mm
子类别:Serial IO/Communication Controllers最大供电电压:1.575 V
最小供电电压:1.425 V标称供电电压:1.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:15 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches:1

RC82540EM 数据手册

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82540EM Gigabit Ethernet Controller  
Networking Silicon  
Datasheet  
Product Features  
PCI Bus  
Host Off-Loading  
PCI Revision 2.3 support for 32-bit wide  
interface at 33 MHz and 66 MHz  
Algorithms that optimally use advanced  
PCI, MWI, MRM, and MRL commands  
MAC Specific  
Transmit and receive IP, TCP, and UDP  
checksum off-loading capabilities  
Transmit TCP segmentation  
Advanced packed filtering  
Jumbo frame support up to 16 KB  
IEEE 802.1q VLAN support with VLAN  
tag insertion, stripping and packet filtering  
for up to 4096 VLAN tags  
Low-latency transmit and receive queues  
IEEE 802.3x-compliant flow-control  
support with software-controllable  
thresholds  
Descriptor ring management hardware for  
Caches up to 64 packet descriptors in a  
transmit and receive  
single burst  
Interrupt coalescing (multiple packets per  
interrupt)  
Jumbo frame support  
Programmable host memory receive  
buffers (256 B to 16 KB) and cache line  
size (16 B to 256 B)  
Manageability  
Wide, optimized internal data path  
Manageability features: SMB port, ASF  
1.0, ACPI, Wake on LAN, and PXE  
On-board SMB port  
Compliance with PCI Power Management  
1.1 and ACPI 2.0 register set compliant  
SNMP and RMON statistic counters  
SDG 3.0, WfM 2.0, and PC2001  
compliance  
architecture  
64 KB configurable Transmit and Receive  
FIFO buffers  
PHY Specific  
Integrated for 10/100/1000 Mb/s operation  
full and half duplex operation  
IEEE 802.3ab Auto-Negotiation support  
IEEE 802.3ab PHY compliance and  
compatibility.  
State-of-the-art DSP architecture  
implements digital adaptive equalization,  
echo cancellation, and cross-talk  
cancellation  
Additional Device  
Four activity and link indication outputs  
that directly drive LEDs  
JTAG (IEEE 1149.1) Test Access Port  
built in silicon  
Internal PLL for clock generation can use  
Automatic detection of cable lengths and  
a 25 MHz crystal  
MDI vs. MDI-X cable at all speeds  
Programmable LED functionality  
Revision 1.5  
November 2004  

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