Datasheet > Q67100-Q1838

Q67100-Q1838

更新时间： 2024-01-14 10:40:47

品牌	Logo	应用领域
英飞凌 - INFINEON		动态存储器
页数	文件大小	规格书
53页	410K
描述
64-MBit Synchronous DRAM

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数据手册

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Q67100-Q1838 数据手册

HYB 39S64400/800/160BT(L)

64-MBit Synchronous DRAM

• High Performance:

• Multiple Burst Read with Single Write

Operation

• Automatic and Controlled Precharge

Command

-7.5 -8

Units

f_CKMAX

t_CK3

133 125 MHz

• Data Mask for Read/Write Control (x4, x8)

• Data Mask for Byte Control (x16)

• Auto Refresh (CBR) and Self Refresh

• Suspend Mode and Power Down Mode

• 4096 Refresh Cycles / 64 ms

7.5

5.4

t_AC3

t_CK2

t_AC2

• Random Column Address every CLK

(1-N Rule)

• Fully Synchronous to Positive Clock Edge

• 0 to 70 °C operating temperature

• Four Banks controlled by BA0 & BA1

• Programmable CAS Latency: 2, 3

• Single 3.3 V ± 0.3 V Power Supply

• LVTTL Interface

• Plastic Packages:

P-TSOPII-54 400mil width (x4, x8, x16)

• Programmable Wrap Sequence: Sequential

or Interleave

• -7.5 version for PC133 3-3-3 application

-8 version for PC100 2-2-2 applications

• Programmable Burst Length: 1, 2, 4, 8

• Full page (optional) for sequential wrap

around

The HYB 39S64400/800/160BT are four bank Synchronous DRAM’s organized as

4 banks × 4MBit ×4, 4 banks × 2 MBit ×8 and 4 banks × 1 Mbit ×16 respectively. These synchron-

ous devices achieve high speed data transfer rates by employing a chip architecture that prefects

multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using

the Infineon advanced 0.2 µm 64 MBit DRAM process technology.

The device is designed to comply with all JEDEC standards set for Synchronous DRAM products,

both electrically and mechanically. All of the control, address, data input and output circuits are

synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur

at higher rates than is possible with standard DRAMs. A sequential and gapless data rate is

possible depending on burst length, CAS latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a

single 3.3 V ± 0.3 V power supply and are available in TSOPII packages.

Data Book

12.99

12 3 4 5 6 7...53

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