Datasheet > Q67100-Q1327

Q67100-Q1327

更新时间： 2024-01-21 15:43:25

品牌	Logo	应用领域
英飞凌 - INFINEON		动态存储器
页数	文件大小	规格书
22页	149K
描述
16 MBit Synchronous DRAM

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数据手册

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Q67100-Q1327 数据手册

16 MBit Synchronous DRAM

(second generation)

HYB 39S16400/800/160AT-8/-10

Advanced Information

• High Performance:

• Multiple Burst Read with Single Write

Operation

CAS latency = 3

-8

125

-10 Units

100 MHz

• Automatic and Controlled Precharge

Command

f_CK

t_CK3

t_AC3

• Data Mask for Read/Write control (× 4, × 8)

• Dual Data Mask for byte control (× 16)

• Auto Refresh (CBR) and Self Refresh

• Suspend Mode and Power Down Mode

• 4096 refresh cycles/64 ms

• Single Pulsed RAS Interface

• Fully Synchronous to Positive Clock Edge

• 0 to 70 °C operating temperature

• Random Column Address every CLK

(1-N Rule)

• Dual Banks controlled by A11 (Bank Select)

• Programmable CAS Latency: 1, 2, 3

• Single 3.3 V ± 0.3 V Power Supply

• LVTTL Interface versions

• Programmable Wrap Sequence: Sequential

or Interleave

• Plastic Packages:

P-TSOPII-44-1 400 mil width (× 4, × 8)

P-TSOPII-50-1 400 mil width (× 16)

• Programmable Burst Length:

1, 2, 4, 8 and full page for Sequential type

1, 2, 4, 8 for Interleave type

The HYB 39S1640x/80x/16xAT are dual bank Synchronous DRAM’s based on the die revisions “B”

and “C” and organized as 2 banks × 2 MBit × 4, 2 banks × 1 MBit × 8 and 2 banks × 512 kBit × 16

respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by

employing a chip architecture that prefetches multiple bits and then synchronizes the output data to

a system clock. The chip is fabricated with SIEMENS advanced 16 MBit DRAM process technology.

The device is designed to comply with all JEDEC standards set for synchronous DRAM products,

both electrically and mechanically. All of the control, address, data input and output circuits are

synchronized with the positive edge of an externally supplied clock.

Operating the two memory banks in an interleaved fashion allows random access operation to occur

at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to

125 MHz is possible depending on burst length, CAS latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single

3.3 V ± 0.3 V power supply and are available in TSOPII packages.

Semiconductor Group

1998-10-01

12 3 4 5 6 7...22

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