Datasheet > PV5G3EA

PV5G3EA

更新时间： 2024-11-18 17:15:39

品牌	Logo	应用领域
尼克森微 - NIKOSEM		/
页数	文件大小	规格书
4页	279K
描述
SOP-8

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中文翻译

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数据手册

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PV5G3EA 数据手册

P-Channel Logic Level Enhancement Mode

Field Effect Transistor

PV5G3EA

NIKO-SEM

SOP-8

Halogen-free & Lead-Free

PRODUCT SUMMARY

V_(BR)DSS

-30V

R_DS(ON)

I_D

8mΩ

-15A

Features

• Pb−Free, Halogen Free and RoHS compliant.

• Low R_DS(on)to Minimize Conduction Losses.

• Ohmic Region Good R_DS(on)Ratio.

• Optimized Gate Charge to Minimize Switching Losses.

• Products Integrated ESD diode with ESD Protected.

G : GATE

D : DRAIN

S : SOURCE

Applications

• Protection Circuits Applications.

• Logic/Load Switch Circuits Applications.

100% UIS Tested

100% Rg Tested

ABSOLUTE MAXIMUM RATINGS (T_A= 25 °C Unless Otherwise Noted)

PARAMETERS/TEST CONDITIONS

Drain-Source Voltage

SYMBOL

V_DS

LIMITS

-30

UNITS

Gate-Source Voltage

V_GS

±20

T_A= 25 °C

T_A= 70 °C

-15

Continuous Drain Current

I_D

-12

Pulsed Drain Current¹

Avalanche Current

Avalanche Energy

I_DM

I_AS

-60

-67

L = 0.1mH

T_A= 25 °C

T_A= 70 °C

E_AS

224

2.9

Power Dissipation³

P_D

1.8

Junction & Storage Temperature Range

T_j, T_stg

-55 to 150

°C

THERMAL RESISTANCE RATINGS

THERMAL RESISTANCE

SYMBOL

TYPICAL

MAXIMUM

UNITS

Junction-to-Ambient²

t ≦10s

Steady-State

R_JA

R_JC

Junction-to-Ambient²

°C / W

Junction-to-Case

¹Pulse width limited by maximum junction temperature.

²The value of R_θJAis measured with the device mounted on 1in²FR-4 board with 2oz. Copper, in a still air

environment with T_A=25°C.

³The Power dissipation is based on R_JAt ≦10s value.

REV1.0

J-K-4

12 3 4

中文翻译

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