Data Sheet
PT7A4402B/4402L
T1/E1 System Synchronizer
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Features
Description
• Supports AT&T TR62411 Stratum 3, 4 and
Stratum 4 Enhanced for DS1 interfaces and for
ETSI ETS 300 011, TBR 4, TBR 12, and TBR
13 for E1 interfaces
PT7A4402B/4402L employs a digital phase-locked loop
(DPLL) to provide timing and synchronizing signals for
multitrunk T1 and E1 primary rate transmission links. The
ST-BUS clock and framing signals are phase-locked to
input reference signals of either 2.048 MHz, 1.544MHz
or 8 kHz.
•
Provides C1.5, C3, C2, C4, C8 and C16 output
clock signals
•
Provides three kinds of 8kHz ST-BUS framing
signals
The PT7A4402B/4402L meets the requirements for
AT&T TR62411 Stratum 3, 4 and Stratum 4 Enhanced,
and ETSI ETS 300 011 in jitter tolerance, jitter transfer,
intrinsic jitter, frequency accuracy, holdover accuracy,
capture range, phase slope and MTIE, etc.
•
•
Two independent reference inputs
Input reference frequency 1.544MHz, 2.048MHz
or 8kHz selectable
•
•
Provides bit error free reference switching and
meets phase slope and MTIE requirements
Normal, Holdover or Free-Run operating modes
available
The PT7A4402B/4402Loperates in Manual orAutomatic
Mode, and in each of the modes, three operating states
are available: Normal, Holdover and Free-Run.
•
•
Automatic reference input impairment monitor
Power supply: 5V (4402B) and 3.3V(4402L)
Ordering Information
Applications
• Synchronization and timing control for multitrunk
T1 and E1 systems
Part Number
PT7A4402BJ
PT7A4402LJ
PT7A4402BJE
PT7A4402LJE
Package
28-Pin PLCC
•
•
ST-BUS clock and frame pulse sources
Primary Trunk Rate Converters
28-Pin PLCC
Lead free 28-Pin PLCC
Lead free 28-Pin PLCC
PT0100(12/05)
Ver:1
1