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PT7A4401C

更新时间: 2024-11-18 21:55:47
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其他 - ETC /
页数 文件大小 规格书
27页 156K
描述
PT7A4401C T1/E1 System Synchronizer

PT7A4401C 数据手册

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Data Sheet  
PT7A4401C T1/E1 System Synchronizer  
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Features  
Introduction  
• Meets jitter requirements for AT&T TR62411  
Stratum 4 and Stratum 4 Enhanced for DS1  
interfaces, and for ETSI ETS300 011 for E1 inter-  
faces  
PT7A4401C is functionally enhanced version of  
PT7A4401B. It has better jitter performance and C16  
whose output duty cycle is independent of 20MHz  
master clock.  
• Provides C1.5, C3, C2, C4, C8 and C16 output  
clock signals  
The PT7A4401C employs a digital phase-locked loop  
(DPLL) to provide timing and synchronizing signals  
for multitrunk T1 and E1 primary rate transmission  
links. It generates the ST-BUS clock and framing sig-  
nals that are phase-locked to input reference signals  
of either 2.048MHz, 1.544MHz or 8kHz.  
• Provides 3 kinds of 8kHz framing signals  
• Selectable 1.544MHz, 2.084MHz or 8kHz input  
reference signals  
• Operates in either Normal or Free-Run states  
• Enhanced in jitter and duty cycle comparing with  
PT7A4401B  
• Package: 28-pin PLCC (PT7A4401CJ)  
The PT7A4401C is compliant with AT&T TR62411  
Stratum 4 and Stratum 4 Enhanced, and ETSI ETS  
300 011. It meets the requirements for jitter tolerance,  
jitter transfer, intrinsic jitter, frequency accuracy, cap-  
ture range and phase slope, etc.  
Applications  
• Synchronization and timing control for multitrunk  
T1 and E1 systems  
• ST-BUS clock and frame pulse sources  
PT0108(09/02)  
Ver:0  
1

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