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PSD913F2V-20U1T PDF预览

PSD913F2V-20U1T

更新时间: 2024-11-25 11:51:19
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
109页 910K
描述
Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 3.3 V

PSD913F2V-20U1T 数据手册

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PSD813F2V PSD854F2V  
Flash in-system programmable (ISP) peripherals  
for 8-bit MCUs, 3.3 V  
NOT FOR NEW DESIGN  
FEATURES SUMMARY  
FLASH IN-SYSTEM PROGRAMMABLE (ISP)  
PERIPHERAL FOR 8-BIT MCUS  
Figure 1. Packages  
DUAL BANK FLASH MEMORIES  
UP TO 2 Mbit OF PRIMARY FLASH  
MEMORY (8 Uniform Sectors, 32K x8)  
UP TO 256 Kbit SECONDARY FLASH  
MEMORY (4 Uniform Sectors)  
Concurrent operation: READ from one  
memory while erasing and writing the  
other  
PQFP52 (M)  
UP TO 256 Kbit of SRAM  
27 RECONFIGURABLE I/O PORTS  
ENHANCED JTAG SERIAL PORT  
PLD WITH MACROCELLS  
Over 3000 Gates of PLD: CPLD and  
DPLD  
CPLD with 16 Output Macrocells (OMCs)  
and 24 Input Macrocells (IMCs)  
DPLD - user defined internal chip select  
decoding  
PLCC52 (J)  
27 INDIVIDUALLY CONFIGURABLE I/O  
PORT PINS  
The can be used for the following functions:  
MCU I/Os  
PLD I/Os  
Latched MCU addess output  
Special funcn I/Os.  
16 of the I/O ports may be configured as  
open-drain outputs.  
TQFP64 (U)  
IN-SYSTEM PROGRAMMING (ISP) WITH  
JT
HIGH ENDURANCE:  
100,000 Erase/WRITE Cycles of Flash  
Memory  
Built-in JTAG compliant serial port allows  
full-chip In-System Programmability  
Efficient manufacturing allow easy  
product testing and programming  
1,000 Erase/WRITE Cycles of PLD  
15 Year Data Retention  
3.3V 10ꢀ SINGLE SUPPLY VOLTAGE  
STANDBY CURRENT AS LOW AS 25µA  
Packages are ECOPACK  
Use low cost FlashLINK cable with PC  
PAGE REGISTER  
®
Internal page register that can be used to  
expand the microcontroller address space  
by a factor of 256  
PROGRAMMABLE POWER MANAGEMENT  
May 2009  
Doc ID 10552 Rev 3  
1/109  
This is information on a product still in production but not recommended for new designs.  

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