Datasheet > PSA1780A_10

PSA1780A_10

更新时间： 2024-09-24 10:04:31

品牌	Logo	应用领域
ZCOMM		/
页数	文件大小	规格书
2页	80K
描述
PHASE LOCKED LOOP

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中文翻译

获取价格

数据手册

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PSA1780A_10 数据手册

PSA1780A

PHASE LOCKED LOOP

14118 Stowe Drive, Suite B | Poway, CA 92064

TEL: (858) 621-2700 | FAX: (858) 486-1927

Rev A1

PHASE NOISE (1 Hz BW, typical)

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

FEATURES

• Frequency Range: 1780 -

1840 MHz

KHz

• Step Size:

•

- Style Package

PLL-24

APPLICATIONS

• Telecommunications

• Satellite

100

1000

10000

100000

Telemetry

•

VALUE

1780 - 1840

UNITS

MHz

PERFORMANCE SPECIFICATIONS

Frequency Range

-106

dBc/Hz

dBc

Phase Noise @ 10 kHz offset (1 Hz BW, typ.)

Harmonic Suppression (2nd, typ.)

Sideband Spurs (typ.)

-15

-65

3±2

dBc

Power Output

dBm

Load Impedance

Step Size

kHz

3.13

Charge Pump Output Current

Switching Speed (typ., adjacent channel)

Startup Lock Time (typ.)

5.5

mSec

°C

-40 to 85

Operating Temperature Range

Package Style

PLL-24

POWER SUPPLY REQUIREMENTS

Supply Voltage (Vcc, nom.)

Vdc

Supply Current (Icc, typ.)

All specifications are typical unless otherwise noted and subject to change without notice.

APPLICATION NOTES

• AN-107 : How to Solder Z-COMM VCOs / PLLs

• AN-202 : PLL Functional Description

NOTES:

Reference Oscillator Signal: 5 MHz<

<100 MHz

Frequency Synthesizer: National Semiconductor - ADF4106

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