PSA0951A

更新时间： 2024-02-06 09:25:37

品牌	Logo	应用领域
ZCOMM		/
页数	文件大小	规格书
2页	76K
描述
LOW COST - HIGH ERFORMANCE PHASE LOCKED LOOP

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中文翻译

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技术参数
数据手册

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PSA0951A 技术参数

是否Rohs认证：	符合	生命周期：	Contact Manufacturer
Reach Compliance Code：	compliant	风险等级：	5.72
Is Samacsys：	N	Base Number Matches：	1

PSA0951A 数据手册

PSA0951A

9939 Via Pasar • San Diego, CA 92126

TEL (858) 621-2700 FAX (858) 621-2722

PHASE LOCKED LOOP

Rev A1

PHASE NOISE (1 Hz BW, typical)

-70

-90

-110

-130

-150

-170

FEATURES

• Frequency Range:

• Step Size:

950

956

MHz

KHz

•

- Style Package

PLL-24

APPLICATIONS

• Basestations

• Satellite Communications

Mobile Radios

1 E+3

10 E+3

100 E+3

1 E+6

•

VALUE

950 - 956

UNITS

MHz

PERFORMANCE SPECIFICATIONS

Frequency Range

-100

dBc/Hz

dBc

Phase Noise @ 10 kHz offset (1 Hz BW, typ.)

Harmonic Suppression (2nd, typ.)

Sideband Spurs (typ.)

-15

-65

dBc

Power Output

2.5±2.5

dBm

Load Impedance

Step Size

Ω

KHz

1250

Charge Pump Output Current

Switching Speed (typ., adjacent channel)

Startup Lock Time (typ.)

µΑ

mSec

°C

-40 to 85

Operating Temperature Range

Package Style

PLL-24

POWER SUPPLY REQUIREMENTS

Supply Voltage (Vcc, nom.)

Vdc

Supply Current (Icc, typ.)

All specifications are typical unless otherwise noted and subject to change without notice.

APPLICATION NOTES

• AN-107 : How to Solder Z-COMM VCOs / PLLs

• AN-200 : Mounting and Grounding of Z-COMM PLLs

• AN-201 : PLL Fundamentals

AN-202 : PLL Functional Description

NOTES:

Reference Oscillator Signal: 5 MHz<f_osc<100 MHz

Frequency Synthesizer: Analog Devices - ADF4106

Page 1

中文翻译

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