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PRMD2

更新时间： 2024-11-20 11:14:55

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
14页	282K
描述
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)Production

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PRMD2 数据手册

PRMD2

50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors

(RET)

14 September 2018

Product data sheet

1. General description

NPN/PNP Resistor-Equipped double Transistors (RET) in a leadless ultra small DFN1412-6

(SOT1268) Surface-Mounted Device (SMD) plastic package.

2. Features and benefits

•

100 mA output current capability

•

Built-in bias resistors

Simplifies circuit design

Reduces component count

Reduces pick and place costs

Low package height of 0.5 mm

AEC-Q101 qualified

3. Applications

•

Digital applications

Cost-saving alternative to BC847/BC857 series in digital applications

Control of IC inputs

Switching loads

4. Quick reference data

Table 1. Quick reference data

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Per transistor, for the PNP transistor with negative polarity

V_CEO

collector-emitter

voltage

open base

I_O

output current

DC current gain

bias resistor 1

bias resistor ratio

100

h_FE

V_CE= 5 V; I_C= 5 mA; T_amb= 25 °C

15.4

0.8

[1]

28.6

1.2

kΩ

R2/R1

[1] See section "Test information" for resistor calculation and test conditions.

12 3 4 5 6 7...14

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