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PPC5777MK0MVU8B PDF预览

PPC5777MK0MVU8B

更新时间： 2024-11-06 02:52:39
品牌 Logo 应用领域
恩智浦 - NXP 时钟以太网：16GBASE-T外围集成电路
页数 文件大小 规格书
168页 1592K
描述
Three main CPUs, single issue, 32-bit CPU core complexes

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中文翻译

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PPC5777MK0MVU8B 技术参数

生命周期：Active包装说明：BGA,
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：5.67具有ADC：YES
其他特性：INCLUDES GTM104, ETHERNET SUPPORT, 74KB(ADDITIONAL RAM)地址总线宽度：32
位大小：32最大时钟频率：40 MHz
DAC 通道：NODMA 通道：YES
外部数据总线宽度：32JESD-30 代码：S-PBGA-B416
长度：27 mmI/O 线路数量：
端子数量：416片上程序ROM宽度：8
最高工作温度：125 °C最低工作温度：-40 °C
PWM 通道：NO封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAYRAM（字节）：413696
ROM（单词）：8388608ROM可编程性：FLASH
筛选级别：ISO 26262座面最大高度：2.55 mm
速度：300 MHz最大供电电压：1.38 V
最小供电电压：1.19 V标称供电电压：1.325 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
宽度：27 mmuPs/uCs/外围集成电路类型：MICROCONTROLLER, RISC
Base Number Matches：1

PPC5777MK0MVU8B 数据手册

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NXP Semiconductors  
Data Sheet: Technical Data  
Document Number: MPC5777M  
Rev. 6, 06/2016  
MPC5777M  
416 TEPBGA  
27mm x 27 mm  
512 TEPBGA  
MPC5777M Microcontroller  
Data Sheet  
25 mm x 25 mm  
• Three main CPUs, single issue, 32-bit CPU core complexes  
(e200z7), one of which is a dedicated lockstep core.  
– Dual phase-locked loops with stable clock domain for  
peripherals and FM modulation domain for  
computational shell  
®
– Power Architecture embedded specification  
compliance  
• Dual crossbar switch architecture for concurrent access to  
peripherals, flash, or RAM from multiple bus masters with  
end-to-end ECC  
• Hardware Security Module (HSM) to provide robust  
integrity checking of flash memory  
• System Integration Unit Lite (SIUL)  
• Boot Assist Module (BAM) supports factory programming  
using serial bootload through ‘UART Serial Boot Mode  
Protocol’. Physical interface (PHY) can be:  
– UART/LIN  
– Instruction set enhancement allowing variable length  
encoding (VLE), encoding a mix of 16-bit and 32-bit  
instructions, for code size footprint reduction  
– Single-precision floating point operations  
– 16 KB Local instruction RAM and 64 KB local data  
RAM  
– 16 KB I-Cache and 4 KB D-Cache  
• I/O Processor, dual issue, 32-bit CPU core complex  
(e200z4), with  
– Power Architecture embedded specification compliance  
– Instruction set enhancement allowing variable length  
encoding (VLE), encoding a mix of 16-bit and 32-bit  
instructions, for code size footprint reduction  
– Single-precision floating point operations  
– Lightweight Signal Processing Auxiliary Processing  
Unit (LSP APU) instruction support for digital signal  
processing (DSP)  
– CAN  
• GTM104 — generic timer module  
• Enhanced analog-to-digital converter system with  
– Twelve separate 12-bit SAR analog converters  
– Ten separate 16-bit Sigma-Delta analog converters  
• Eight deserial serial peripheral interface (DSPI) modules  
• Two Peripheral Sensor Interface (PSI5) controllers  
• Three LIN and three UART communication interface  
(LINFlexD) modules (6 total)  
– 16 KB Local instruction RAM and 64 KB local data  
RAM  
– LINFlexD_0 is a Master/Slave  
– 8 KB I-Cache  
• 8640 KB on-chip flash  
– LINFlexD_1, LINFlexD_2, LINFlexD_14,  
LINFlexD_15, and LINFlexD_16 are Masters  
• Four modular controller area network (MCAN) modules  
and one time-triggered controller area network  
(M-TTCAN)  
– Supports read during program and erase operations, and  
multiple blocks allowing EEPROM emulation  
• 404 KB on-chip general-purpose SRAM including 64 KB  
standby RAM (+ 192 KB data RAM included in the  
CPUs). Of this 404 KB, 64 KB can be powered by a  
separate supply so the contents of this portion can be  
preserved when the main MCU is powered down.  
• Multichannel direct memory access controllers (eDMA): 2  
x 64 channels per eDMA (128 channels total)  
• Triple Interrupt controller (INTC)  
• External Bus Interface (EBI)  
– Dual routing of accesses to EBI  
– Access path determined by access address  
– Access path downstream of PFLASH controller  
– Allows EBI accesses to share buffer and prefetch  
capabilities of internal flash  
– Allows internal flash accesses to be remapped to  
memories connected to EBI  
NXP reserves the right to change the detail specifications as may be required to permit  
improvements in the design of its products.  
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