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PPC405GPR3BB266 PDF预览

PPC405GPR3BB266

更新时间: 2024-11-27 10:00:51
品牌 Logo 应用领域
AMCC /
页数 文件大小 规格书
58页 1211K
描述
32-BIT, 266.66 MHz, RISC PROCESSOR, PBGA456, 35 X 35 MM, PLASTIC, EBGA-456

PPC405GPR3BB266 数据手册

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Part Number 405GPr  
Revision 2.00 – December 2, 2004  
Data Sheet  
405GPr  
Power PC 405GPr Embedded Processor  
Features  
®
- Synchronous or asynchronous PCI Bus  
interface  
• PowerPC 405 32-bit RISC processor core  
operating up to 400MHz with 16KB I- and  
D-caches  
- Internal or external PCI Bus Arbiter  
• Synchronous DRAM (SDRAM) interface operating  
up to 133MHz  
• Ethernet 10/100Mbps (full-duplex) support with  
media independent interface (MII)  
- 32-bit interface for non-ECC applications  
• Programmable interrupt controller supports 13  
external and 19 internal edge triggered or level-  
sensitive interrupts  
- 40-bit interface serves 32 bits of data plus 8  
check bits for ECC applications  
• Programmable timers  
• 4KB on-chip memory (OCM)  
• Two serial ports (16550 compatible UART)  
• One IIC interface  
• External peripheral bus  
- Flash ROM/Boot ROM interface  
- Direct support for 8-, 16-, or 32-bit SRAM and  
external peripherals  
• General purpose I/O (GPIO) available  
• Supports JTAG for board level testing  
- Up to eight devices  
• Internal processor local Bus (PLB) runs at SDRAM  
interface frequency  
- External Mastering supported  
• DMA support for external peripherals, internal  
UART and memory  
• Supports PowerPC processor boot from PCI  
memory  
- Scatter-gather chaining supported  
- Four channels  
• Unique software-accessible 64-bit chip ID number  
(ECID).  
• PCI Revision 2.2 compliant interface (32-bit, up to  
66MHz)  
Description  
Designed specifically to address embedded  
applications, the PowerPC 405GPr (PPC405GPr)  
provides a high-performance, low-power solution that  
interfaces to a wide range of peripherals by  
incorporating on-chip power management features  
and lower power dissipation requirements.  
ports, IIC interface, and general purpose I/O.  
Technology: CMOS SA-27E, 0.18 µm  
(0.11 µm L )  
eff  
Package: 456-ball (35mm or 27mm) enhanced plastic  
ball grid array (E-PBGA) in both leaded and lead-free  
versions  
This chip contains a high-performance RISC  
processor core, SDRAM controller, PCI bus interface,  
Ethernet interface, control for external ROM and  
peripherals, DMA with scatter-gather support, serial  
Power (typical): 0.72W at 266MHz  
AMCC  
1

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